EMISSION DRIVER, DISPLAY APPARATUS INCLUDING THE SAME AND METHOD OF DRIVING DISPLAY APPARATUS

    公开(公告)号:US20230197016A1

    公开(公告)日:2023-06-22

    申请号:US18111197

    申请日:2023-02-17

    CPC classification number: G09G3/3291 G09G2310/08 G09G2330/04

    Abstract: An emission driver includes a plurality of stages. A stage of the plurality of stages receives a start signal, a first clock signal, a second clock signal, a protection signal, a first gate power voltage and a second gate power voltage and outputs an emission signal. The stage of the plurality of stages includes a pull-up switching element connected between a first gate power voltage terminal which receives the first gate power voltage and an emission signal output terminal which outputs the emission signal, a pull-down switching element connected between a second gate power voltage terminal which receives the second gate power voltage and the emission signal output terminal and a protection switching element which applies the first gate power voltage to a control electrode of the pull-down switching element in response to the protection signal.

    GATE DRIVER AND DISPLAY DEVICE HAVING THE SAME

    公开(公告)号:US20240062702A1

    公开(公告)日:2024-02-22

    申请号:US18125135

    申请日:2023-03-23

    Abstract: Provided is a gate driver comprising an inverter inverting a start signal to generate an inverted start signal, a first driver including a first stage generating a bias gate signal to initialize a light emitting element of each of pixels in response to the inverted start signal, and a second driver including a second stage generating a write gate signal to apply data voltages to the pixels in response to the start signal. Accordingly, the gate driver may generate a plurality of gate signals using one start signal. In addition, since the gate driver generates a write gate signal and a bias gate signal using one start signal, a bias operation and a light emitting element initialization operation may be performed in a self-scan period without adding the start signal. Further, a size of the gate driver may be reduced, and accordingly, the gate driver may be efficiently disposed.

    DISPLAY APPARATUS HAVING A NOTCH
    4.
    发明申请

    公开(公告)号:US20220157241A1

    公开(公告)日:2022-05-19

    申请号:US17588520

    申请日:2022-01-31

    Abstract: A display apparatus includes a substrate which includes a first pixel area and a second pixel area. A third pixel area is spaced apart from the second pixel area. A notch peripheral area is adjacent to the first, second and third pixel areas. A plurality of pixels are provided in the first, second and third pixel areas. A first scan line is disposed on the substrate. The first scan line includes a first portion disposed in the second pixel area, a second portion disposed in the third pixel area, and a third portion which connects the first portion to the second portion. The third portion is disposed in the notch peripheral area. A second scan line is disposed on the substrate in the first pixel area. A surface area of the first scan line is from about 90% to about 110% of a surface area of the second scan line.

    EMISSION DRIVER, DISPLAY APPARATUS INCLUDING THE SAME AND METHOD OF DRIVING DISPLAY APPARATUS

    公开(公告)号:US20210366408A1

    公开(公告)日:2021-11-25

    申请号:US17321825

    申请日:2021-05-17

    Abstract: An emission driver includes a plurality of stages. A stage of the plurality of stages receives a start signal, a first clock signal, a second clock signal, a protection signal, a first gate power voltage and a second gate power voltage and outputs an emission signal. The stage of the plurality of stages includes a pull-up switching element connected between a first gate power voltage terminal which receives the first gate power voltage and an emission signal output terminal which outputs the emission signal, a pull-down switching element connected between a second gate power voltage terminal which receives the second gate power voltage and the emission signal output terminal and a protection switching element which applies the first gate power voltage to a control electrode of the pull-down switching element in response to the protection signal.

    DISPLAY PANEL TEST CIRCUIT
    7.
    发明申请

    公开(公告)号:US20210286002A1

    公开(公告)日:2021-09-16

    申请号:US17191581

    申请日:2021-03-03

    Abstract: A display panel test circuit includes a first transistor connected to a first data line and receiving a red lighting test signal, a second transistor connected to the first data line and receiving a blue lighting test signal, a third transistor connected to a second data line and receiving a first green lighting test signal, a fourth transistor connected to a third data line and receiving the red lighting test signal, a fifth transistor connected to the third data line and receiving the blue lighting test signal, a sixth transistor connected to a fourth data line and receiving a second green lighting test signal, a seventh transistor connected to the second data line and receiving a crack test signal, and an eighth transistor connected to the fourth data line and receiving the crack test signal. The display panel test circuit performs one or more tests on a display panel.

    DISPLAY APPARATUS HAVING A NOTCH
    8.
    发明申请

    公开(公告)号:US20190304366A1

    公开(公告)日:2019-10-03

    申请号:US16260775

    申请日:2019-01-29

    Abstract: A display apparatus includes a substrate which includes a first pixel area and a second pixel area. A third pixel area is spaced apart from the second pixel area. A notch peripheral area is adjacent to the first, second and third pixel areas. A plurality of pixels are provided in the first, second and third pixel areas. A first scan line is disposed on the substrate. The first scan line includes a first portion disposed in the second pixel area, a second portion disposed in the third pixel area, and a third portion which connects the first portion to the second portion. The third portion is disposed in the notch peripheral area. A second scan line is disposed on the substrate in the first pixel area. A surface area of the first scan line is from about 90% to about 110% of a surface area of the second scan line.

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