公开(公告)号：US20220352295A1

公开(公告)日：2022-11-03

申请号：US17866561

申请日：2022-07-18

Applicant: Samsung Display Co., Ltd.

Inventor： Joonho OH ,  Seungjae Kang ,  Myung-Seok Kwon ,  Yun-Tae Kim ,  Jin-Ki Kim ,  Hasook Kim

IPC: H01L27/32 ,  G09G3/36 ,  G09G3/3225 ,  G02F1/1362

Abstract: A display device includes a display substrate, a main circuit board, and first and second connection circuit boards. The display substrate includes a base layer, an insulating layer on the base layer, a first signal line on the base layer, a second signal line on the base layer, a first pad exposed from the insulating layer and connected to the first signal line, and a second pad connected to a side surface of the second signal line and disposed on a side surface and a bottom surface of the base layer. The first connection circuit board electrically connects the first pad and the main circuit board, and the second connection circuit board electrically connects the second pad and the main circuit board.

公开(公告)号：US09190008B2

公开(公告)日：2015-11-17

申请号：US13940444

申请日：2013-07-12

Applicant: Samsung Display Co., Ltd.

Inventor： Ki-Hyun Pyun ,  Jang-Hoon Kwak ,  Jung-Hoon Ku ,  Jin-Ki Kim ,  Seung-Woon Shin ,  Jun-Ho Hwang

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G3/3677 ,  G09G2330/12

Abstract: A gate driving module includes a gate driver and a gate signal generator. The gate driver generates a vertical start signal, a plurality of gate clock signals and a plurality of inverse gate clock signals based on a vertical start control signal, a plurality of gate clock control signals, a gate on voltage, a first gate off voltage and a second gate off voltage. The number of the gate clock signals is P. The number of the inverse gate clock signals is P. The number of the gate clock control signals is P. P is a positive integer equal to or greater than two. The gate signal generator generates a gate signal based on the vertical start signal, the gate clock signals and the inverse gate clock signals.

Abstract translation: 栅极驱动模块包括栅极驱动器和栅极信号发生器。 栅极驱动器基于垂直启动控制信号，多个栅极时钟控制信号，栅极导通电压，第一栅极截止电压和第一栅极截止电压产生垂直起始信号，多个栅极时钟信号和多个反向栅极时钟信号，以及 第二栅极关断电压。 栅极时钟信号的数量为P.反向栅极时钟信号的数量为P.栅极时钟控制信号的数量为P.P为等于或大于2的正整数。 栅极信号发生器基于垂直起始信号，栅极时钟信号和反向栅极时钟信号产生栅极信号。

公开(公告)号：US20140253418A1

公开(公告)日：2014-09-11

申请号：US13940444

申请日：2013-07-12

Applicant: Samsung Display Co., Ltd.

Inventor： KI-HYUN PYUN ,  Jang-Hoon Kwak ,  Jung-Hoon Ku ,  Jin-Ki Kim ,  Seung-Woon Shin ,  Jun-HO Hwang

IPC: G09G3/36 ,  H03K17/00

CPC classification number: G09G3/3696 ,  G09G3/3677 ,  G09G2330/12

Abstract: A gate driving module includes a gate driver and a gate signal generator. The gate driver generates a vertical start signal, a plurality of gate clock signals and a plurality of inverse gate clock signals based on a vertical start control signal, a plurality of gate clock control signals, a gate on voltage, a first gate off voltage and a second gate off voltage. The number of the gate clock signals is P. The number of the inverse gate clock signals is P. The number of the gate clock control signals is P. P is a positive integer equal to or greater than two. The gate signal generator generates a gate signal based on the vertical start signal, the gate clock signals and the inverse gate clock signals.

Abstract translation: 栅极驱动模块包括栅极驱动器和栅极信号发生器。 栅极驱动器基于垂直启动控制信号，多个栅极时钟控制信号，栅极导通电压，第一栅极截止电压和第一栅极截止电压产生垂直起始信号，多个栅极时钟信号和多个反向栅极时钟信号，以及 第二栅极关断电压。 栅极时钟信号的数量为P.反向栅极时钟信号的数量为P.栅极时钟控制信号的数量为P.P为等于或大于2的正整数。 栅极信号发生器基于垂直起始信号，栅极时钟信号和反向栅极时钟信号产生栅极信号。

公开(公告)号：US12127453B2

公开(公告)日：2024-10-22

申请号：US17866561

申请日：2022-07-18

Applicant: Samsung Display Co., Ltd.

Inventor： Joonho Oh ,  Seungjae Kang ,  Myung-Seok Kwon ,  Yun-Tae Kim ,  Jin-Ki Kim ,  Hasook Kim

IPC: H10K59/131 ,  G02F1/1362 ,  G09G3/3225 ,  G09G3/36

CPC classification number: H10K59/131 ,  G02F1/136286 ,  G09G3/3225 ,  G09G3/3648

Abstract: A display device includes a display substrate, a main circuit board, and first and second connection circuit boards. The display substrate includes a base layer, an insulating layer on the base layer, a first signal line on the base layer, a second signal line on the base layer, a first pad exposed from the insulating layer and connected to the first signal line, and a second pad connected to a side surface of the second signal line and disposed on a side surface and a bottom surface of the base layer. The first connection circuit board electrically connects the first pad and the main circuit board, and the second connection circuit board electrically connects the second pad and the main circuit board.