公开(公告)号：US10290270B2

公开(公告)日：2019-05-14

申请号：US15069766

申请日：2016-03-14

Applicant: Samsung Display Co., Ltd.

Inventor： Yong-ju Jeong ,  Jae-kook Kim ,  Seung-woon Shin ,  Choongseob Oh ,  Hyoungbin Lim ,  Minsung Choi

IPC: G09G3/36 ,  G09G3/34 ,  G09G5/06

Abstract: There is provided a display apparatus comprising: a backlight configured to output a first and a second light having a first and second color during a first and second field of a frame; a mapper configured to map an input image signal into a first and a second mapping data corresponding to the first and second light; a compensator configured to compensate a first and a second color mapping data on a basis of a first and a second DCC compensation data so as to generate a first and second color output image data; and a liquid crystal panel comprising a transmissive sub pixel configured to modulate the first and second light on a basis of the first and second color output data to display a first image having the first color and a second image having the second color.

公开(公告)号：US09852707B2

公开(公告)日：2017-12-26

申请号：US14517036

申请日：2014-10-17

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Woon Shin ,  Jae-Kook Kim ,  JeongJin Park ,  Choongseob Oh ,  Hyoungbin Lim ,  Yong-Ju Jeong ,  Minsung Choi

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0219

Abstract: A display apparatus including: gate lines extending in a first direction; data lines extending in a second direction intersecting the first direction; pixels connected to corresponding ones of the gate lines and data lines; a gate driver to drive the gate lines in response to a gate clock signal; a data driver to drive the data lines; a memory to store charge share signals corresponding to the gate lines; a timing controller controlling the data driver and the gate driver, in response to an externally input control signal and an image signal, and to output a gate pulse signal to the gate lines; and a clock generator configured to generate the gate clock signal in response to the gate pulse signal. The timing controller is configured to output the gate pulse signals according to the charge share signals.