Abstract:
A display apparatus includes a display panel configured to display an image. The display panel includes a plurality of display areas. A display panel driver is configured to output a driving signal to the display panel. A backlight unit is configured to provide light to the display panel. A luminance compensating part is configured to generate a backlight compensating signal having different compensating values according to a distance between the display panel driver and the display areas of the display panel.
Abstract:
There is provided a display apparatus comprising: a backlight configured to output a first and a second light having a first and second color during a first and second field of a frame; a mapper configured to map an input image signal into a first and a second mapping data corresponding to the first and second light; a compensator configured to compensate a first and a second color mapping data on a basis of a first and a second DCC compensation data so as to generate a first and second color output image data; and a liquid crystal panel comprising a transmissive sub pixel configured to modulate the first and second light on a basis of the first and second color output data to display a first image having the first color and a second image having the second color.
Abstract:
A liquid crystal display device includes a liquid crystal display panel including a plurality of pixels, a voltage generator generating a gate on voltage and a gate off voltage, a gate driver generating a gate signal provided to the pixel using the gate on voltage and the gate off voltage, and providing the gate signal to the pixels, a data driver providing a data signal to the pixels, and a timing controller generating control signals that control the gate driver and the data driver. Each of the pixels includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. A voltage level of the gate off voltage provided to the red sub-pixel, a voltage level of the gate off voltage provided to the green sub-pixel, and a voltage level of the gate off voltage provided to the blue sub-pixel are different from one another.
Abstract:
A display apparatus includes a display panel including left-eye pixels and right-eye pixels, a three-dimensional controller which separates a first image signal into left-eye and right-eye image signals, outputs a second image signal such that the left-eye image signal is applied to the left-eye pixels during a left-eye frame, a black image signal corresponding to a black data is applied to the right-eye pixels during the left-eye frame, the black image signal is applied to the left-eye pixels during a right-eye frame, and the right-eye image signal is applied to the right-eye pixels during the right-eye frame, and an image display controller which controls the second image signal in response to a control signal, where the left-eye pixels are alternately arranged with the right-eye pixels in the unit of two pixels in a first direction and in the unit of a predetermined number of pixels in the second direction.
Abstract:
A liquid crystal display device includes a liquid crystal display panel including a plurality of pixels, a voltage generator generating a gate on voltage and a gate off voltage, a gate driver generating a gate signal provided to the pixel using the gate on voltage and the gate off voltage, and providing the gate signal to the pixels, a data driver providing a data signal to the pixels, and a timing controller generating control signals that control the gate driver and the data driver. Each of the pixels includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. A voltage level of the gate off voltage provided to the red sub-pixel, a voltage level of the gate off voltage provided to the green sub-pixel, and a voltage level of the gate off voltage provided to the blue sub-pixel are different from one another.
Abstract:
A display apparatus including: gate lines extending in a first direction; data lines extending in a second direction intersecting the first direction; pixels connected to corresponding ones of the gate lines and data lines; a gate driver to drive the gate lines in response to a gate clock signal; a data driver to drive the data lines; a memory to store charge share signals corresponding to the gate lines; a timing controller controlling the data driver and the gate driver, in response to an externally input control signal and an image signal, and to output a gate pulse signal to the gate lines; and a clock generator configured to generate the gate clock signal in response to the gate pulse signal. The timing controller is configured to output the gate pulse signals according to the charge share signals.