公开(公告)号：US20200035182A1

公开(公告)日：2020-01-30

申请号：US16393018

申请日：2019-04-24

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeonseok BAE ,  Haengwon PARK ,  Jungdeok SEO

IPC: G09G3/36 ,  G11C19/28

Abstract: A gate driving circuit includes a charge part which charges a charge node with a clock signal having a first high voltage for a first period, an output part which charges an output node with the first high voltage in response to a first voltage of the charge node for the first period, and outputs a second voltage of the output node as a gate signal, a first discharge part which discharges the second voltage to a first off voltage in response to a clock bar signal having a second high voltage for a second period following the first period, and a second discharge part which discharges the first voltage to the second off voltage for the second period. The second off voltage is set to one of a first level lower than a level of the first off voltage and a second level lower than the first level.

公开(公告)号：US20180286304A1

公开(公告)日：2018-10-04

申请号：US15944207

申请日：2018-04-03

Applicant: Samsung Display Co., LTD.

Inventor： Haengwon PARK ,  Hyeonseok BAE ,  Myoung Jun CHAI ,  Seunghoon HAN ,  Dongwon PARK

IPC: G09G3/22 ,  G02F1/1362 ,  H04N5/202

Abstract: A display apparatus includes a display panel, a gate driver and a data driver. The display panel displays an image and includes first sub-pixels which display a first color, second sub-pixels which display a second color different from the first color, first gate lines to which only the first sub-pixels are connected, second gate lines to which only the second sub-pixels are connected, and data lines. The gate sequentially applies first gate signals only to the first gate lines during a first duration of a first frame, and sequentially applies second gate signals only to the second gate lines during a second duration of the first frame, where the second duration is subsequent to the first duration. The data driver outputs data voltages to the data lines based on input image data in synchronization with a driving sequence of the first and second gate lines.