公开(公告)号：US11315452B2

公开(公告)日：2022-04-26

申请号：US17069254

申请日：2020-10-13

Applicant: Samsung Display Co., Ltd.

Inventor： Gwang Soo Ahn ,  Sung Soo Choi ,  Jong Jae Lee

IPC: G09G3/00 ,  G09G3/20

Abstract: A display apparatus includes a display panel, a timing controller and a power management integrated circuit (PMIC). The timing controller is to control an operation of the display panel and to store a plurality of fault patterns to be displayed on the display panel to represent that a plurality of defective phenomena have occurred. The PMIC is to supply a first power supply voltage to the timing controller and to monitor whether the plurality of defective phenomena have occurred. When a first defective phenomenon among the plurality of defective phenomena is sensed, the PMIC is to store first fault data and to shut down the display panel. When the first defective phenomenon is sensed, the timing controller is to control the display panel to display a first fault pattern corresponding to the first defective phenomenon among the plurality of fault patterns before the display panel is shut down.

公开(公告)号：US11538374B2

公开(公告)日：2022-12-27

申请号：US17181309

申请日：2021-02-22

Applicant: Samsung Display Co., Ltd.

Inventor： Sung Soo Choi ,  Dae-Sik Lee ,  Ji Youn Seo ,  Gwang Soo Ahn ,  Jong Jae Lee ,  Geun Hyuk Choi

IPC: G09G3/20 ,  G09G3/00

Abstract: A power voltage generator includes a voltage sensor and a power controller. The voltage sensor is configured to sense a first voltage in a first charge sharing period of a gate clock signal and a second voltage in a second charge sharing period of the gate clock signal. The power breaker is configured to disconnect a power based on the first voltage and the second voltage.

公开(公告)号：US10762858B2

公开(公告)日：2020-09-01

申请号：US15812451

申请日：2017-11-14

Applicant: Samsung Display Co., Ltd.

Inventor： Hong-Kyu Kim ,  Myeong Su Kim ,  Po-Yun Park ,  Gwang Soo Ahn

IPC: G09G3/36 ,  G09G3/20 ,  G09G5/00

Abstract: A display device includes a display panel including: a plurality of pixels; and a signal controller which generates, on a frame-by-frame basis, a display signal based on an input image signal and a control signal from an outside. The signal controller includes a memory which stores a preset image signal, a receiver which receives the control signal, a clock signal modulator which generates an internal clock signal having a first frequency during a blank period, which is determined based on the control signal in a frame period, and a data processor which reads the preset image signal from the memory in response to the internal clock signal for an image processing.