DISPLAY DEVICE
    1.
    发明申请

    公开(公告)号:US20250107372A1

    公开(公告)日:2025-03-27

    申请号:US18974430

    申请日:2024-12-09

    Abstract: A display device includes a substrate on which a display area including a plurality of pixels and a non-display area surrounding the display area are defined, a first voltage line disposed on the substrate in the non-display area, where the first voltage line provides a first voltage to the pixels, a second voltage line disposed on the substrate in the non-display area, where the second voltage line provides a second voltage to the pixels, and a first demux circuit area and a second demux circuit area disposed on the substrate in the non-display area, where the first demux circuit area and the second demux circuit area transmit data signals to the pixels. The first voltage line passes an area between the first demux circuit area and the second demux circuit area.

    DISPLAY DEVICE
    2.
    发明公开
    DISPLAY DEVICE 审中-公开

    公开(公告)号:US20240304152A1

    公开(公告)日:2024-09-12

    申请号:US18666836

    申请日:2024-05-17

    CPC classification number: G09G3/3275 H10K59/121 G09G2310/0297

    Abstract: A display device may include a substrate including a circular display area and a non-display area, a plurality of pixels including a first pixel and a second pixel disposed on the display area of the substrate, a first sub-demux circuit connected to the first pixel and disposed on the non-display area, a second sub-demux circuit connected to the second pixel and disposed on the non-display area, a first connection line connected to the first sub-demux circuit and the second sub-demux circuit and disposed on the non-display area to transfer first and second data input signals to the first and second sub-demux circuits, and a plurality of gate stages connected to the pixels and disposed on the non-display area to transfer gate signals to the pixels. Some of the gate stages are disposed between the first sub-demux circuit and the second sub-demux circuit.

    DISPLAY DEVICE
    3.
    发明公开
    DISPLAY DEVICE 审中-公开

    公开(公告)号:US20240099062A1

    公开(公告)日:2024-03-21

    申请号:US18520227

    申请日:2023-11-27

    CPC classification number: H10K59/121 H10K59/131

    Abstract: A display device includes a circular display area and a non-display area surrounding the circular display area. The display device may further include a load matcher disposed adjacent to an edge of the circular display area in the circular display area, a pixel disposed in the circular display area, spaced apart from the non-display area by the load matcher, and connected to the load matcher, and a repair pixel disposed adjacent to the edge of the circular display area in the non-display area, and connected to the pixel.

    SCAN DRIVER AND DISPLAY DEVICE INCLUDING THE SAME

    公开(公告)号:US20250087169A1

    公开(公告)日:2025-03-13

    申请号:US18826486

    申请日:2024-09-06

    Abstract: A scan driver includes a plurality of stages sequentially connected to each other. Each of the plurality of stages includes first and second output transistors and first to fourth control transistors. The second control transistor is connected between a second node and a first voltage terminal and to an input terminal and operates in response to a start signal or a previous carry signal provided through the input terminal. Each of the first and second output transistors and the first, third, and fourth control transistors is a first type, and the second control transistor is a second type different from the first type.

    DRIVER AND DISPLAY DEVICE
    5.
    发明申请

    公开(公告)号:US20240386838A1

    公开(公告)日:2024-11-21

    申请号:US18403346

    申请日:2024-01-03

    Abstract: A driver is disposed in a display panel, and includes a plurality of stages. At least one stage of the plurality of stages includes an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal, and inverters which generate an output signal based on a voltage of the first node. At least one of the inverters includes a p-type metal-oxide-semiconductor (“PMOS”) transistor and an n-type metal-oxide-semiconductor (“NMOS”) transistor connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage. A first active region of the PMOS transistor includes a material different from a material of a second active region of the NMOS transistor.

    DISPLAY DEVICE
    6.
    发明申请

    公开(公告)号:US20220208933A1

    公开(公告)日:2022-06-30

    申请号:US17533563

    申请日:2021-11-23

    Abstract: A display device includes a substrate on which a display area including a plurality of pixels and a non-display area surrounding the display area are defined, a first voltage line disposed on the substrate in the non-display area, where the first voltage line provides a first voltage to the pixels, a second voltage line disposed on the substrate in the non-display area, where the second voltage line provides a second voltage to the pixels, and a first demux circuit area and a second demux circuit area disposed on the substrate in the non-display area, where the first demux circuit area and the second demux circuit area transmit data signals to the pixels. The first voltage line passes an area between the first demux circuit area and the second demux circuit area.

    DISPLAY DEVICE
    7.
    发明申请

    公开(公告)号:US20220367601A1

    公开(公告)日:2022-11-17

    申请号:US17689317

    申请日:2022-03-08

    Abstract: A display device includes a display area having a curved outer edge, a non-display area extended along the curved outer edge of the display area, the non-display area including a driver, a first non-display area including a first fan-out line having a first resistivity value; and a second non-display area extended along the curved outer edge of the display area and in a direction away from the first non-display area, the second non-display area including a first connection line which connects the driver to the first fan-out line, the first connection line having a second resistivity value less than the first resistivity value of the first fan-out line.

    DISPLAY DEVICE
    8.
    发明申请

    公开(公告)号:US20220102436A1

    公开(公告)日:2022-03-31

    申请号:US17332139

    申请日:2021-05-27

    Abstract: A display device includes a circular display area and a non-display area surrounding the circular display area. The display device may further include a load matcher disposed adjacent to an edge of the circular display area in the circular display area, a pixel disposed in the circular display area, spaced apart from the non-display area by the load matcher, and connected to the load matcher, and a repair pixel disposed adjacent to the edge of the circular display area in the non-display area, and connected to the pixel.

    DISPLAY APPARATUS HAVING A TRANSMITTING AREA

    公开(公告)号:US20220020840A1

    公开(公告)日:2022-01-20

    申请号:US17228636

    申请日:2021-04-12

    Abstract: A display apparatus includes a substrate including a transmitting area, a display area surrounding the transmitting area, a first non-display area disposed between the transmitting area and the display area, and a second non-display area surrounding the display area. A plurality of pixels is arranged in the display area. A set of 2n connection wirings (where n is a positive integer) is disposed in the first non-display area and each of the 2n connection wirings extends along at least a part of an edge of the transmitting area. Each of a plurality of voltage wirings extends in a first direction and is connected to at least some of pixels disposed in a common row from among the plurality of pixels. Each of the plurality of voltage wirings is connected to one of the 2n connection wirings.

    GATE DRIVER
    10.
    发明申请

    公开(公告)号:US20250104596A1

    公开(公告)日:2025-03-27

    申请号:US18675139

    申请日:2024-05-28

    Abstract: A gate driver includes a plurality of stages. At least one of the stages includes a control circuit configured to control a first control node in response to a first carry clock signal, a node separation transistor connected between the first control node and a second control node, a carry output circuit configured to output a carry signal in response to a voltage of the second control node, and a plurality of gate output circuits configured to output a plurality of gate signals having different timings in response to the voltage of the second control node.

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