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公开(公告)号：US20240096276A1
公开(公告)日：2024-03-21
申请号：US18465486
申请日：2023-09-12
发明人： Minwoo Byun , Junyong AN , Soongi KWON , Junyoung MIN , Junwon CHOI , Chaehan HYUN
IPC分类号： G09G3/3225 , G09G3/32
CPC分类号： G09G3/3225 , G09G3/32 , G09G2300/0426
摘要： Each of a plurality of stages of a gate driving circuit includes a first node controller configured to control voltage levels of a first node and a second node, a second node controller configured to control a voltage level of a third node, and a first output unit configured to output the first voltage or the second voltage as a gate signal according to the voltage levels of the second node and the third node. The first node controller includes a single gate transistor having one gate and a dual gate transistor having a pair of gates disposed in different layers with a semiconductor disposed therebetween.
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公开(公告)号：US20230413624A1
公开(公告)日：2023-12-21
申请号：US18242713
申请日：2023-09-06
发明人： Junyoung MIN , Jaewon KIM , Junwon CHOI
IPC分类号： H10K59/131 , H10K59/65 , H10K59/121
CPC分类号： H10K59/131 , H10K59/65 , H10K59/1213 , H01L29/7869
摘要： A display device includes: a substrate in which a transmission area, a display area, a non-display area and the display area, and a peripheral area are defined; pixels arranged on the display area; initialization gate lines and compensation gate lines extending along pixel rows; gate driving circuits disposed on the peripheral area; and gate connection lines disposed on the non-display area. A k-th gate driving circuit among the gate driving circuits simultaneously drives m-th and (m+1)-th initialization gate lines and n-th and (n+1)-th compensation gate lines. First portions of the n-th and (n+1)-th compensation gate lines and second portions of the n-th and (n+1)-th compensation gate lines, which are physically apart from each other by the transmission area, are electrically connected to each other through a first gate connection line among gate connection lines.
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公开(公告)号：US20240357883A1
公开(公告)日：2024-10-24
申请号：US18413258
申请日：2024-01-16
发明人： Junwon CHOI , Myeonghee SEO , Hwayoung SONG , Junyoung MIN
IPC分类号： H10K59/131 , B60K35/22 , H10K59/121
CPC分类号： H10K59/131 , B60K35/22 , H10K59/1216 , B60K2360/1523 , B60K2360/332
摘要： A display panel includes a substrate including a display area including a sub-pixel and a non-display area outside the display area, the non-display area including a pad area, a demultiplexer circuit area which is disposed in the non-display area and transmits a data signal to the sub-pixel, a compensation capacitor area between the pad area and the demultiplexer circuit area, the compensation capacitor area including a plurality of compensation capacitors each including a first electrode and a second electrode on the first electrode, and a plurality of fan-out lines extending from the pad area to the compensation capacitor area.
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公开(公告)号：US20230240107A1
公开(公告)日：2023-07-27
申请号：US18159635
申请日：2023-01-25
发明人： Junyoung MIN , Wonkyu KWAK , Huigyeong YUN , Junwon CHOI , Jihyun KA , Yangwan KIM , Myeonghee SEO
IPC分类号： H10K59/131
CPC分类号： H10K59/1315 , H10K59/124
摘要： A display device includes: a substrate including a display area and a non-display area including a pad area; an inorganic insulating layer disposed on the substrate and including a first inorganic insulating layer, a second inorganic insulating layer, and a third inorganic insulating layer; a light-emitting element layer disposed on the inorganic insulating layer and including a light-emitting element overlapping the display area in a plan view; a gate wiring overlapping the display area in the plan view, extending in a first direction and disposed between the first inorganic insulating layer and the second inorganic insulating layer; and a fanout wiring extending in a direction toward the display area from the pad area and disposed between the second inorganic insulating layer and the third inorganic insulating layer, where a sheet resistance of the gate wiring is lower than a sheet resistance of the fanout wiring.
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