公开(公告)号：US20170323598A1

公开(公告)日：2017-11-09

申请号：US15584600

申请日：2017-05-02

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jinwoo PARK ,  Chaehan HYUN ,  Kimyeong EOM ,  Seungwoo SUNG ,  Junghoon SHIM ,  Minkyu WOO

IPC: G09G3/3233 ,  H01L51/50 ,  H01L51/52

CPC classification number: G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2300/0876 ,  G09G2310/0262 ,  G09G2320/02 ,  G09G2320/043 ,  H01L27/3265 ,  H01L27/3276 ,  H01L51/50 ,  H01L51/5203

Abstract: An organic light-emitting display includes a first pixel adjacent to a second pixel and a plurality of driving voltage lines to apply driving voltages to the first pixel and the second pixel. The driving voltage lines extend in a first direction crossing the first pixel and the second pixel and a second direction crossing the first direction. Each of the first and second pixels includes a first driving transistor and a second driving transistor that are symmetrical to each other with respect to a boundary between the first pixel and the second pixel, and a first compensation transistor and a second compensation transistor that are asymmetrical to each other with respect to the boundary.

公开(公告)号：US20240096276A1

公开(公告)日：2024-03-21

申请号：US18465486

申请日：2023-09-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Minwoo Byun ,  Junyong AN ,  Soongi KWON ,  Junyoung MIN ,  Junwon CHOI ,  Chaehan HYUN

IPC: G09G3/3225 ,  G09G3/32

CPC classification number: G09G3/3225 ,  G09G3/32 ,  G09G2300/0426

Abstract: Each of a plurality of stages of a gate driving circuit includes a first node controller configured to control voltage levels of a first node and a second node, a second node controller configured to control a voltage level of a third node, and a first output unit configured to output the first voltage or the second voltage as a gate signal according to the voltage levels of the second node and the third node. The first node controller includes a single gate transistor having one gate and a dual gate transistor having a pair of gates disposed in different layers with a semiconductor disposed therebetween.