公开(公告)号：US20130193461A1

公开(公告)日：2013-08-01

申请号：US13771637

申请日：2013-02-20

Applicant: Samsung Display Co., LTD.

Inventor： Su-Jeong KIM ,  Jang-Kun SONG ,  Sung-Hwan HONG ,  Kee-Bum PARK ,  Seon-Ah CHO ,  Hye-Ran YOU ,  Su-Han WOO ,  Jae-Jin LYU ,  Eun CHO

IPC: G02F1/1343

CPC classification number: G02F1/13439 ,  G02F1/133707 ,  G02F1/1393 ,  G02F2001/134345 ,  G02F2201/123

Abstract: An array substrate includes a lower substrate, a switching element and a pixel electrode. In the lower substrate, unit pixel areas are each divided into a plurality of domains. The switching element is disposed on the lower substrate and transmits a pixel signal. The pixel electrode is disposed on the unit pixel area and is electrically connected to the switching element. The pixel electrode includes a plurality of slit portions disposed thereon. A portion of the slit portions is longitudinally extended in a zigzag shape along different directions in correspondence with the domains.

Abstract translation: 阵列基板包括下基板，开关元件和像素电极。 在下基板中，单位像素区域分为多个域。 开关元件设置在下基板上并透射像素信号。 像素电极设置在单位像素区域上并与开关元件电连接。 像素电极包括设置在其上的多个狭缝部。 狭缝部分的一部分沿着与畴相对应的不同方向以锯齿形状纵向延伸。

公开(公告)号：US20130095618A1

公开(公告)日：2013-04-18

申请号：US13709707

申请日：2012-12-10

Applicant: Samsung Display Co., Ltd. ,  Sang Cheol SHIN

Inventor： Yoon-Sung UM ,  Hoon KIM ,  Hye-Ran YOU ,  Jae-Jin LYU ,  Seung-Beom PARK

IPC: H01L29/66

CPC classification number: H01L29/6675 ,  G02F1/13624 ,  G02F2001/134345 ,  H01L27/1288

Abstract: In a thin film transistor, first and second thin film transistors are connected to an Nth gate line and an Mth data line, and first and second sub pixel electrodes are connected to the first and second thin film transistors, respectively. A third thin film transistor includes a gate electrode connected to an (N+1)th gate line, a semiconductor layer overlapping with the gate electrode, a source electrode connected to the second sub pixel electrode and partially overlapping with the gate electrode, and a drain electrode facing the source electrode. A first auxiliary electrode is connected to the drain electrode and arranged on the same layer as the first and second sub pixel electrodes. An opposite electrode is arranged on the same layer as the gate line and at least partially overlaps with the first auxiliary electrode with at least one insulating layer disposed therebetween.

Abstract translation: 在薄膜晶体管中，第一和第二薄膜晶体管连接到第N栅极线和第M数据线，第一和第二子像素电极分别连接到第一和第二薄膜晶体管。 第三薄膜晶体管包括连接到第（N + 1）栅极线的栅电极，与栅电极重叠的半导体层，连接到第二子像素电极并与栅电极部分重叠的源极， 漏电极面对源电极。 第一辅助电极连接到漏电极并且设置在与第一和第二子像素电极相同的层上。 相对电极布置在与栅极线相同的层上，并且与第一辅助电极至少部分重叠，并且其间设置有至少一个绝缘层。