公开(公告)号：US20240072037A1

公开(公告)日：2024-02-29

申请号：US18231928

申请日：2023-08-09

Applicant: STMicroelectronics SA

Inventor： Johan BOURGEAT ,  Yohann SOLARO

IPC: H01L27/02 ,  H01L27/146

CPC classification number: H01L27/0255 ,  H01L27/0288 ,  H01L27/0296 ,  H01L27/14634

Abstract: An electronic device includes a doped semiconductor substrate of a first conductivity type. A first doped well of a second conductivity type opposite to the first conductivity type extends into the doped semiconductor substrate from a surface thereof. A second doped well of the first conductivity type is located in the first well. A third electrically-insulating well is located in the second well. A fourth doped well of the first conductivity type is located in the third well. First, second, and third doped regions of the first conductivity type are respectively located in the doped semiconductor substrate, the second doped well and the fourth doped well. The first, second, and third doped regions have doping levels greater than a doping level of the doped semiconductor substrate. A fourth doped region the second conductivity type is located in the fourth doped well adjacent the second doped region.

公开(公告)号：US20190267367A1

公开(公告)日：2019-08-29

申请号：US16406534

申请日：2019-05-08

Applicant: STMicroelectronics SA

Inventor： Johan BOURGEAT

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/06

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.

公开(公告)号：US20240072036A1

公开(公告)日：2024-02-29

申请号：US18232032

申请日：2023-08-09

Applicant: STMicroelectronics SA

Inventor： Yohann SOLARO ,  Johan BOURGEAT

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L29/7436

Abstract: An electronic device includes a doped semiconductor substrate of a first conductivity type. First and second doped wells are provided, separated from each other by trench isolation, within the doped semiconductor substrate. At least one first region and at least one second region are respectively located in the first and second doped wells, with each first and second region having a doping level higher than a doping level of the first and second doped wells. The trench isolation penetrates into the first and second doped wells and extends laterally between the first region and second region. A third region laterally extends between the first and second doped wells at a location under the insulating trench. The third region has a doping level lower than the doping level of the first and second doped wells.

公开(公告)号：US20210193648A1

公开(公告)日：2021-06-24

申请号：US17191250

申请日：2021-03-03

Applicant: STMicroelectronics SA

Inventor： Johan BOURGEAT

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/06

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.