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公开(公告)号：US20180313699A1
公开(公告)日：2018-11-01
申请号：US15957999
申请日：2018-04-20
摘要： A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
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公开(公告)号：US20220308615A1
公开(公告)日：2022-09-29
申请号：US17702362
申请日：2022-03-23
发明人： Barbaro MARANO , Mario CHIRICOSTA
摘要： A cell includes a first pair and a second pair of MOS transistors. Each of the first pair and second pair of MOS transistors have drain electrodes coupled to a respective common input node. Each of the first pair and second pair of MOS transistors includes a diode-connected MOS transistor and a latched MOS transistor. The latched MOS transistors of the first pair and second pair of MOS transistors have cross-coupled gate and drain electrodes. Source electrodes of the diode connected MOS transistors from the first pair and second pair of MOS transistors are coupled to a first current output common node to output a current to a first current collecting circuit. Source source electrodes of the latched MOS transistors of the first pair and second pair of MOS transistors are coupled to a second current output common node to output a current to a second current collecting circuit.
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公开(公告)号：US20200264648A1
公开(公告)日：2020-08-20
申请号：US16867299
申请日：2020-05-05
摘要： A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference formed by a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.
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公开(公告)号：US20160347606A1
公开(公告)日：2016-12-01
申请号：US14962945
申请日：2015-12-08
发明人： Giuseppe BRUNO , Sebastiano CONTI , Mario CHIRICOSTA , Michele VAIANA , Calogero Marco IPPOLITO , Mario MAIORE , Daniele CASELLA
IPC分类号： B81B7/00
CPC分类号： B81B7/007 , B81B7/02 , B81B2201/0264 , B81B2201/0292 , B81B2207/094 , G01L19/0092 , G01N27/223 , H01L23/3121 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： A packaged sensor assembly includes: a packaging structure, having at least one opening; a humidity sensor and a pressure sensor, which are housed inside the packaging structure and communicate fluidically with the outside through the opening, and a control circuit, operatively coupled to the humidity sensor and to the pressure sensor; wherein the humidity sensor and the control circuit are integrated in a first chip, and the pressure sensor is integrated in a second chip distinct from the first chip and bonded to the first chip.
摘要翻译： 包装传感器组件包括：具有至少一个开口的包装结构; 湿度传感器和压力传感器，其容纳在包装结构内并通过开口与外部流体连通;以及控制电路，可操作地耦合到湿度传感器和压力传感器; 其中所述湿度传感器和所述控制电路集成在第一芯片中，并且所述压力传感器集成在与所述第一芯片不同的第二芯片中并且被结合到所述第一芯片。
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