公开(公告)号：US20030107428A1

公开(公告)日：2003-06-12

申请号：US10290030

申请日：2002-11-07

Applicant: STMicroelectronics S.r.l.

Inventor： Osama Khouri ,  Andrea Pierin ,  Dario Soltesz ,  Guido Torelli

IPC: G05F003/02

CPC classification number: G11C5/145 ,  H02M3/073 ,  H02M2001/0032 ,  H02M2003/075 ,  H02M2003/077 ,  Y02B70/16

Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages comprising an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

Abstract translation: 连接在第一参考电压和输出端子之间的电荷泵电路包括至少两个级，包括连接在所述第一参考电压和所述输出端子之间的基本电荷泵电路，以及连接在所述输出端子和相应控制端子之间的调节电路 的至少两个阶段。 该电路被设置为根据从连接到输出端子的负载吸收的电流来选择这些基本级的适当组合。

公开(公告)号：US20020196171A1

公开(公告)日：2002-12-26

申请号：US10060076

申请日：2002-01-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Osama Khouri ,  Andrea Pierin ,  Stefano Gregori ,  Guido Torelli

IPC: H03M001/14

CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

Abstract: An analog-to-digital conversion method and device for a multilevel non-volatile memory devicethat includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the least significant bits. The first step is completed within a time interval corresponding to the rise transient of the gate voltage, and the second step is initiated at the end of the transient. Also disclosed is a scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different nullbit-layersnull, which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is achieved by using a simple error control code providing single-bit correction, regardless of the number of bits stored in a single cell.

Abstract translation: 用于多电平非易失性存储器设备的模数转换方法和装置包括多电平存储器单元。 该方法包括转换存储单元中包含的最高有效位的第一步骤，随后转换最低有效位的第二步骤。 在对应于栅极电压的上升瞬变的时间间隔内完成第一步，并且在瞬态结束时启动第二步。 还公开了一种用于多电平闪存中的错误控制编码的方案。 存储在单个存储器单元中的n位被组织在彼此独立的不同“位层”中。 针对每个位层分别执行错误校正。 通过使用提供单位校正的简单误差控制代码来实现单个存储器单元中的任何故障的校正，而不管存储在单个单元中的位数。

公开(公告)号：US20020099988A1

公开(公告)日：2002-07-25

申请号：US10003474

申请日：2001-10-25

Applicant: STMicroelectronics S.r.l.

Inventor： Khouri Osama ,  Stefano Gregori ,  Andrea Pierin ,  Rino Micheloni ,  Sergio Coronini ,  Guido Torelli

IPC: G11C029/00 ,  G06F007/02 ,  H03M013/00

CPC classification number: G11C27/005 ,  G11C7/062 ,  G11C11/5642 ,  G11C16/28 ,  G11C2207/063

Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.