公开(公告)号：US20220137133A1

公开(公告)日：2022-05-05

申请号：US17504139

申请日：2021-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Rohit GOEL ,  Anand Kumar MISHRA ,  Rajnish GARG

IPC: G01R31/3185

Abstract: An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.

公开(公告)号：US20230062144A1

公开(公告)日：2023-03-02

申请号：US17898239

申请日：2022-08-29

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Namerita KHANNA ,  Rajnish GARG ,  Rohit Kumar GUPTA

IPC: H04L7/033 ,  H03K19/21 ,  H03K3/037

Abstract: A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.