公开(公告)号：US12243937B2

公开(公告)日：2025-03-04

申请号：US17711597

申请日：2022-04-01

Applicant: STMicroelectronics France ,  STMicroelectronics International N.V.

Inventor： Matthieu Nongaillard ,  Thomas Oheix

IPC: H01L29/778 ,  H01L27/12 ,  H01L29/20 ,  H01L29/205 ,  H01L29/872

Abstract: The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.

公开(公告)号：US12302625B2

公开(公告)日：2025-05-13

申请号：US17709080

申请日：2022-03-30

Applicant: STMicroelectronics France ,  STMicroelectronics International N.V.

Inventor： Matthieu Nongaillard ,  Thomas Oheix

IPC: H10D80/20 ,  H01L25/07 ,  H10D30/47

Abstract: The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

公开(公告)号：US12249644B2

公开(公告)日：2025-03-11

申请号：US17058117

申请日：2019-05-07

Applicant: STMicroelectronics International N.V.

Inventor： Matthieu Nongaillard ,  Thomas Oheix

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20

Abstract: An enhancement-mode high-electron-mobility transistor comprises a structure including a stack made of III-V semiconductor materials defining an interface and capable of forming a conduction layer in the form of a two-dimensional electron gas layer; a source electrode and a drain electrode forming an electrical contact with the conduction layer; and a gate electrode arranged on top of the structure, between the source electrode and the drain electrode. The structure comprises a bar that is arranged below the gate electrode and passes through the interface of the stack. The bar comprises two semiconductor portions exhibiting opposite types of doping, defining a p-n junction in proximity to the interface.