公开(公告)号：US10292259B2

公开(公告)日：2019-05-14

申请号：US15142213

申请日：2016-04-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Laurent Marechal ,  Richard Rembert ,  Jerome Lopez

IPC: H02K1/02 ,  H05K1/02

Abstract: An electronic device disclosed herein includes a first conductor layer, a first nonconducting layer, and a second conductor layer in a stacked arrangement. A signal carrying conductive via is formed in the first nonconducting layer and extends between the first conductor layer and the second conductor layer. A shielding conductive via is formed in the first nonconducting layer, is not electrically coupled to the signal carrying conductive via, and substantially completely surrounds the signal carrying conductive via in spaced apart relation thereto.

公开(公告)号：US11101188B2

公开(公告)日：2021-08-24

申请号：US16551241

申请日：2019-08-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Olivier Franiatte ,  Richard Rembert

IPC: H01L23/04 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L21/60 ,  H01L21/603

Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

公开(公告)号：US20170318664A1

公开(公告)日：2017-11-02

申请号：US15142213

申请日：2016-04-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Laurent Marechal ,  Richard Rembert ,  Jerome Lopez

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/10

CPC classification number: H05K1/0251 ,  H05K1/0222

Abstract: An electronic device disclosed herein includes a first conductor layer, a first nonconducting layer, and a second conductor layer in a stacked arrangement. A signal carrying conductive via is formed in the first nonconducting layer and extends between the first conductor layer and the second conductor layer. A shielding conductive via is formed in the first nonconducting layer, is not electrically coupled to the signal carrying conductive via, and substantially completely surrounds the signal carrying conductive via in spaced apart relation thereto.

公开(公告)号：US11923256B2

公开(公告)日：2024-03-05

申请号：US17378398

申请日：2021-07-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Olivier Franiatte ,  Richard Rembert

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/04 ,  H01L23/498 ,  H01L21/60 ,  H01L21/603

CPC classification number: H01L23/04 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/5385 ,  H01L2021/60022 ,  H01L21/603

Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

公开(公告)号：US20210343609A1

公开(公告)日：2021-11-04

申请号：US17378398

申请日：2021-07-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Olivier Franiatte ,  Richard Rembert

IPC: H01L23/04 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498

Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

公开(公告)号：US20200075436A1

公开(公告)日：2020-03-05

申请号：US16551241

申请日：2019-08-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Olivier Franiatte ,  Richard Rembert

IPC: H01L23/04 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.