公开(公告)号：US12124713B2

公开(公告)日：2024-10-22

申请号：US18057390

申请日：2022-11-21

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francesco Bombaci ,  Andrea Tosoni

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0622 ,  G06F3/0665 ,  G06F3/0679

Abstract: A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.