公开(公告)号：US09685350B2

公开(公告)日：2017-06-20

申请号：US14193267

申请日：2014-02-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Xu Sheng Bao ,  Kang Chen

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L21/485 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

公开(公告)号：US09620557B2

公开(公告)日：2017-04-11

申请号：US14974002

申请日：2015-12-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Seng Guan Chow ,  Lee Sun Lim ,  Rui Huang ,  Xu Sheng Bao ,  Ma Phoo Pwint Hlaing

IPC: H01L21/768 ,  H01L27/146 ,  B81C1/00 ,  H01L25/16 ,  H01L31/0203

CPC classification number: H01L27/1469 ,  B81C1/0023 ,  H01L21/76898 ,  H01L25/165 ,  H01L25/167 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L31/0203 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

公开(公告)号：US20160104731A1

公开(公告)日：2016-04-14

申请号：US14974002

申请日：2015-12-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Seng Guan Chow ,  Lee Sun Lim ,  Rui Huang ,  Xu Sheng Bao ,  Ma Phoo Pwint Hlaing

IPC: H01L27/146 ,  H01L21/768 ,  B81C1/00 ,  H01L31/0203 ,  H01L25/16

CPC classification number: H01L27/1469 ,  B81C1/0023 ,  H01L21/76898 ,  H01L25/165 ,  H01L25/167 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L31/0203 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

Abstract translation: 半导体器件具有含有透明或半透明材料的衬底。 衬垫安装到衬底上。 第一半导体管芯具有有源区和电连接到有源区的第一导电通孔。 有源区域可以包括响应于通过衬底接收的光的传感器。 第一管芯安装到间隔件上，其中有源区域位于间隔件中的开口上方并朝向衬底。 密封剂沉积在第一裸片和衬底上。 在密封剂和第一模具上形成互连结构。 互连结构通过第一导电通孔电连接到有源区。 具有第二导电通孔的第二半导体管芯可以被安装到第一管芯，其中第一导电通孔电连接到第二导电通孔。

公开(公告)号：US20140252573A1

公开(公告)日：2014-09-11

申请号：US14193267

申请日：2014-02-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Xu Sheng Bao ,  Kang Chen

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L21/485 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Abstract translation: 半导体器件具有邻近第一导电层设置的第一导电层和半导体管芯。 密封剂沉积在第一导电层和半导体管芯上。 绝缘层形成在密封剂，半导体管芯和第一导电层之上。 在绝缘层上形成第二导电层。 第一导电层的第一部分电连接到VSS并形成接地平面。 第一导电层的第二部分电连接到VDD并形成电源平面。 第一导电层，绝缘层和第二导电层构成去耦电容器。 在绝缘层和第一导电层上形成包括第二导电层的迹线的微带线。 第一导电层设置在嵌入的虚设裸片，互连单元或模块化PCB单元上。