公开(公告)号：US20130049461A1

公开(公告)日：2013-02-28

申请号：US13336000

申请日：2011-12-23

申请人： SHI-PIAO LUO ,  HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： SHI-PIAO LUO ,  HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H02J4/00

CPC分类号： H05K1/0248 ,  H03K5/1534 ,  H03K19/00346 ,  H04L25/0278 ,  H05K1/0231 ,  H05K1/0246 ,  H05K2201/10015 ,  Y10T307/25

摘要： A circuit topology for multiple loads includes a driving terminal, first and second signal receiving terminals, and a capacitor. The driving terminal is connected to a node through a first transmission line. The node is connected to the first and second signal receiving terminals through second and third transmission lines. The second transmission line is longer than the third transmission line, and a difference between lengths of the second and third transmission lines is greater than a product of a transmission speed and a rise time of signals from the driving terminal. A first terminal of the capacitor is connected to the third transmission line. A second terminal of the capacitor is grounded. A distance between the capacitor and the second signal receiving terminal is less than a distance between the capacitor and the node.

摘要翻译： 用于多个负载的电路拓扑包括驱动端子，第一和第二信号接收端子以及电容器。 驱动终端通过第一传输线连接到节点。 节点通过第二和第三传输线连接到第一和第二信号接收终端。 第二传输线比第三传输线长，并且第二传输线和第三传输线的长度之间的差大于来自驱动终端的信号的传输速度和上升时间的乘积。 电容器的第一端子连接到第三传输线。 电容器的第二个端子接地。 电容器和第二信号接收端子之间的距离小于电容器和节点之间的距离。

公开(公告)号：US20120030639A1

公开(公告)日：2012-02-02

申请号：US12961908

申请日：2010-12-07

申请人： JIA-LU YE ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： JIA-LU YE ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/82

摘要： A computing device and a method selects a signal transmission line from a circuit board, computes an actual length of each line segment of the selected signal transmission line, and computes an actual distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. If each actual length is less than or equal to a corresponding reference length and each actual distance is more than or equal to a corresponding reference distance, the device and method determines a design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is more than a corresponding reference length, or if any actual distance is less than a corresponding reference distance, the device and method determines the design of the signal transmission line does not satisfy the design standards.

摘要翻译： 计算装置和方法从电路板选择信号传输线，计算所选择的信号传输线的每个线段的实际长度，并且计算所选信号传输线的每个线段与对应线之间的实际距离 每个相邻信号传输线的段。 如果每个实际长度小于或等于对应的参考长度，并且每个实际距离大于或等于相应的参考距离，则设备和方法确定所选信号传输线的设计满足设计标准。 否则，如果任何实际长度大于相应的参考长度，或者如果任何实际距离小于相应的参考距离，则设备和方法确定信号传输线的设计不符合设计标准。

公开(公告)号：US20120026707A1

公开(公告)日：2012-02-02

申请号：US12872652

申请日：2010-08-31

申请人： SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H05K7/00

CPC分类号： H05K1/0245 ,  H05K1/0243

摘要： A printed circuit board includes first and second layers, a control chip, bonding pads, and several electronic elements. The bonding pads can be selectively applied to interconnect the first and second layers, and the control chip with any of the electronic elements in a simple layout.

摘要翻译： 印刷电路板包括第一层和第二层，控制芯片，焊盘和几个电子元件。 可以选择性地施加接合焊盘以以简单的布局将第一层和第二层以及控制芯片与任何电子元件互连。

公开(公告)号：US20120185819A1

公开(公告)日：2012-07-19

申请号：US13244625

申请日：2011-09-25

申请人： ZHENG SHAN ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： ZHENG SHAN ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.

摘要翻译： 在使用计算装置验证印刷电路板（PCB）布局的方法中，从计算装置的存储装置获得PCB模拟文件，并且根据PCB仿真文件在显示装置上显示PCB图像。 PCB图像包括多个信号线和开关电压调节器节点（SVRN）。 从PCB图像中选择要检查的SVRN，并搜索SVRN周围的所有信号线。 该方法计算所选择的SVRN与所搜索的信号线之间的布局距离，并且生成图形窗口界面以定位其布局距离等于或小于最小距离的信号线。 该方法通过将布局距离增加到最小距离来进一步修改定位信号线的布局以满足布局设计规范。

公开(公告)号：US20120167027A1

公开(公告)日：2012-06-28

申请号：US13172858

申请日：2011-06-30

申请人： YA-LING HUANG ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： YA-LING HUANG ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： An electronic device and a method for checking layout distance of a printed circuit board (PCB) including presetting a checking condition to determine a reference layer. A high speed signal path is selected from a PCB design file, and a layer where the selected high speed signal path is located can be determined A reference layer of the determined layer is determined according to the checking condition, and a split line of the reference layer is determined. A shortest distance between each segment of the selected high speed signal path and the split line is calculated. If the shortest distance between a segment and the split line is less than the standard distance, layout of the segment is determined to be invalid.

摘要翻译： 一种用于检查印刷电路板（PCB）的布局距离的电子设备和方法，包括预设检查条件以确定参考层。 可以从PCB设计文件中选择高速信号路径，并且可以确定所选择的高速信号路径所在的层。根据检查条件确定确定层的参考层，并且确定参考的分割线 层被确定。 计算所选择的高速信号路径的每个段与分割线之间的最短距离。 如果段与分割线之间的最短距离小于标准距离，则段的布局被确定为无效。

公开(公告)号：US20120017191A1

公开(公告)日：2012-01-19

申请号：US13085432

申请日：2011-04-12

申请人： HAN-LONG CHEN ,  SHI-PIAO LUO ,  CHENG-HSIEN LEE ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： HAN-LONG CHEN ,  SHI-PIAO LUO ,  CHENG-HSIEN LEE ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A computing device and a method involves selection of one or more transmission lines from a printed circuit board (PCB) layout file, reading a transmission line from the one or more selected transmission lines, and determining neighboring anti-pads of the read transmission line in the PCB layout file. The computing device and method further determine an actual distance between the read transmission line and a neighboring anti-pad. If the actual distance is less than a preset standard distance, the computing device and method determine that the read transmission line and the neighboring anti-pad do not satisfy design requirements, and highlight the read transmission line and the neighboring anti-pad, to prompt a user to amend design of the read transmission line and the neighboring anti-pad.

摘要翻译： 计算装置和方法包括从印刷电路板（PCB）布局文件中选择一条或多条传输线，从一条或多条所选传输线读取传输线，以及确定读传输线的相邻抗焊盘 PCB布局文件。 计算设备和方法进一步确定读取传输线与相邻反焊盘之间的实际距离。 如果实际距离小于预设的标准距离，则计算设备和方法确定读取传输线路和相邻的反焊盘不满足设计要求，并突出显示读取传输线路和相邻的反焊盘，以提示 用户修改读取传输线的设计和相邻的反焊盘。

公开(公告)号：US20120273254A1

公开(公告)日：2012-11-01

申请号：US13217626

申请日：2011-08-25

申请人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H01B5/00

CPC分类号： H05K1/111 ,  H05K1/0242 ,  H05K1/025 ,  H05K2201/09736 ,  Y02P70/611

摘要： A pad includes a first mating section and a second mating section. The first mating section includes a first horizontal plane and a first inclined plane. The second mating section includes a second horizontal plane and a second inclined plane. The first mating section is a copper foil capable of being connected to a wire. The second mating section is made of insulating material. The first inclined plane and the second inclined plane are bonded together.

摘要翻译： 垫包括第一配合部分和第二配合部分。 第一配合部分包括第一水平面和第一倾斜平面。 第二配合部分包括第二水平面和第二倾斜平面。 第一配合部分是能够连接到电线的铜箔。 第二配合部分由绝缘材料制成。 第一倾斜平面和第二倾斜平面结合在一起。

公开(公告)号：US20110094783A1

公开(公告)日：2011-04-28

申请号：US12647396

申请日：2009-12-25

申请人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H05K1/16

CPC分类号： H05K1/0253 ,  H05K1/181 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611

摘要： A printed circuit board (PCB) includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path.

摘要翻译： 印刷电路板（PCB）包括信号平面和参考平面。 信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。 参考平面为通过无源元件和传输线传输的信号提供返回路径。 在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。

公开(公告)号：US20120007688A1

公开(公告)日：2012-01-12

申请号：US12960321

申请日：2010-12-03

申请人： HUA-LI ZHOU ,  MING WEI ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： HUA-LI ZHOU ,  MING WEI ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H01P3/08

CPC分类号： H05K1/0245 ,  H05K2201/09727

摘要： A printed circuit board includes an insulation layer and a signal layer attached to the insulation layer. The signal layer includes a pair of differential transmission lines. Width W of each of the differential transmission lines is changed according to change of space S between the differential transmission lines, based on the following formula: W = C   1 × H × ( C   2 × H 0.8  W 0 + T ) C   3 ×  C   4 × S 0 H - 1 1 - C   3 ×  C   4 × S H - 1.25  T In above formula, C1=7.475, C2=5.98, C3=0.48, C4=−0.96, H is a thickness of the insulation layer, W0 is an original width of each of the differential transmission lines, and S0 is an original space between the differential transmission lines, and T is a thickness of each of the differential transmission lines.

摘要翻译： 印刷电路板包括绝缘层和附着到绝缘层的信号层。 信号层包括一对差动传输线。 差分传输线的宽度W根据以下公式根据差分传输线之间的空间S的变化而改变：W = C 1 / H×（C 2 2×H 0.8 W 0 + 在上式中，C 1 = 7.475，C 2 = 5.98，C 3 = C 9，C 3 = 0.48，C4 = -0.96，H是绝缘层的厚度，W0是差分传输线的原始宽度，S0是差动传输线之间的原始空间，T是各个差分传输线的厚度 差动传输线。

公开(公告)号：US20120241201A1

公开(公告)日：2012-09-27

申请号：US13107950

申请日：2011-05-15

申请人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H05K1/09

CPC分类号： H05K1/025 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/09727

摘要： A circuit board includes a substrate and a copper layer positioned on the substrate. The copper layer includes a BGA area and a non-BGA area, and includes traces. The widths of the traces in the BGA area are smaller than the widths of the traces in the non-BGA area, the dielectric coefficient of the substrate in the BGA area is greater than the dielectric coefficient of the substrate in the non-BGA area for keeping the impedance of the traces consistent in the BGA area and in the non-BGA area.

摘要翻译： 电路板包括基板和位于基板上的铜层。 铜层包括BGA区域和非BGA区域，并且包括痕迹。 BGA区域中的迹线的宽度小于非BGA区域中的迹线的宽度，BGA区域中的衬底的介电系数大于非BGA区域中衬底的介电系数， 保持BGA区域和非BGA区域的轨迹阻抗一致。