公开(公告)号：US11188486B2

公开(公告)日：2021-11-30

申请号：US16697122

申请日：2019-11-26

申请人： SHENZHEN GOODIX TECHNOLOGY CO., LTD.

发明人： Zhibing Liang ,  Yifan Li ,  Zekai Chen

IPC分类号： G06F13/38 ,  G06F13/28 ,  G06F13/12 ,  G06F13/16 ,  G06F13/32

摘要： The present disclosure relates to the technical field of a multi-chip system, and provides a master chip, a salve chip, and an inter-chip DMA transmission system. The master chip is connected to the slave chip through at least one first transmission channel (17) and a second transmission channel (18). The master chip includes a DMA controller (2) and an MCU (3). For each of the first transmission channels, when it is detected that any first transmission channel (17) is in an idle state, the MCU (3) configures one of a plurality of first peripherals (12) of the slave chip into a DMA mode. The DMA controller (2) is configured to receive, through the first transmission channel (17), a DMA request (req_s_0-req_s_N) generated by the first peripheral (12) in the DMA mode, and obtain a DMA data of the first peripheral (12) through the second transmission channel (18).

公开(公告)号：US11113098B2

公开(公告)日：2021-09-07

申请号：US16697111

申请日：2019-11-26

申请人： SHENZHEN GOODIX TECHNOLOGY CO., LTD.

发明人： Zhibing Liang ,  Yifan Li ,  Zekai Chen

IPC分类号： G06F9/30 ,  G06F13/26 ,  G06F9/48 ,  G06F9/38

摘要： The present disclosure relates to the field of a multi-chip system, and provides an interrupt processing method, a master chip, a slave chip, and a multi-chip system. An interrupt processing method is applied to a master chip and includes: when an interrupt transport request sent by a slave chip through an interrupt line is detected, obtaining all current interrupt requests (irq_s_1-irq_s_N) of the slave chip, the interrupt request (irq_s_1_-irq_s_N) is generated by a first peripheral (4) of the slave chip; obtaining an interrupt subroutine corresponding to each of the interrupt requests (irq_s_1-irq_s_N), and processing the corresponding interrupt request (irq_s_1-irq_s_N) by using the interrupt subroutine. In the embodiments of the present disclosure, all the interrupt requests (irq_s_1-irq_s_N) of the slave chip are mapped to the master chip, so that the interrupt processing flow of the peripheral on the slave chip is simplified.