公开(公告)号：US20020171577A1

公开(公告)日：2002-11-21

申请号：US10141846

申请日：2002-05-10

申请人： SEIKO EPSON CORPORATION

发明人： Shoichiro Kasahara ,  Chisato Akiyama ,  Fumikazu Komatsu

IPC分类号： H04L017/02 ,  G08C019/12

CPC分类号： G06F13/385

摘要： A macrocell MC1 including a physical-layer circuit in accordance with USB 2.0 or the like is placed at a corner of an integrated circuit device ICD. Data terminals DP and DM are placed in an I/O region IOR1 along a side SD1; and power terminals PVDD, PVSS, XVDD, and XVSS and clock terminals XI and XO of a clock generation circuit and a sampling clock circuit are placed in an I/O region IOR2 along a side SD2. An interface region and a macrocell MC2 including user-specified logic are provided along a side SD3. A reception circuit is placed on a DR1 side of IOR1, a clock generation circuit is placed on a DR2 side of IOR2, and a sampling clock generation circuit is placed on the DR1 side of the reception circuit and also the DR2 side of the clock generation circuit. A transmission circuit is placed on the DR2 side of the reception circuit and on the DR1 side of the data terminals DP and DM.

摘要翻译： 包括根据USB 2.0等的物理层电路的宏单元MC1被放置在集成电路器件ICD的角落处。 数据端子DP和DM沿着侧面SD1放置在I / O区域IOR1中; 并且时钟发生电路和采样时钟电路的电源端子PVDD，PVSS，XVDD和XVSS以及时钟端子XI和XO沿着侧面SD2放置在I / O区域IOR2中。 沿着侧面SD3提供包括用户指定逻辑的接口区域和宏单元MC2。 接收电路放置在IOR1的DR1侧，时钟发生电路放置在IOR2的DR2侧，采样时钟产生电路位于接收电路的DR1侧，时钟生成的DR2侧 电路。 传输电路放置在接收电路的DR2侧和数据端子DP和DM的DR1侧。

公开(公告)号：US20020172151A1

公开(公告)日：2002-11-21

申请号：US10142066

申请日：2002-05-10

申请人： SEIKO EPSON CORPORATION

发明人： Akira Nakada ,  Akira Abe ,  Shoichiro Kasahara

IPC分类号： H04J001/16

CPC分类号： G06F13/4072 ,  H04L7/033

摘要： There are provided a transmission circuit capable of stabilizing high-speed data transfer by driving current, a data transfer control device, and electronic equipment. An HS current driver (transmission circuit) included in a data transfer control device has a current source connected between a first power supply AVDD and a node ND, and switching devices SW1 to SW3, one ends of which are connected to the node ND. The other end of the switching device SW1 is connected to a DP terminal. The other end of the switching device SW2 is connected to a DM terminal. The other end of the switching device SW3 is connected to a DA terminal. The DA terminal is connected to a second power supply AVSS inside or outside the transmission circuit. The transmission circuit is configured so that impedances of each current path from the node ND through the switching devices SW1 to SW3 become substantially equal when the switching device is turned on. This prevents an increase in the voltage of the node ND in a non-signal-transmission period.

摘要翻译： 提供了能够通过驱动电流来稳定高速数据传输的传输电路，数据传输控制装置和电子设备。 包括在数据传输控制装置中的HS电流驱动器（发送电路）具有连接在第一电源AVDD和节点ND之间的电流源以及一端连接到节点ND的开关装置SW1〜SW3。 开关装置SW1的另一端连接到DP端子。 开关装置SW2的另一端连接到DM端子。 开关装置SW3的另一端连接到DA端子。 DA端子连接到传输电路内部或外部的第二电源AVSS。 发送电路被配置为使得当开关装置导通时，从节点ND到开关装置SW1至SW3的每个电流路径的阻抗变得基本相等。 这防止在非信号传输时段中节点ND的电压增加。

公开(公告)号：US20020173090A1

公开(公告)日：2002-11-21

申请号：US10142030

申请日：2002-05-10

申请人： SEIKO EPSON CORPORATION

发明人： Akira Nakada ,  Shoichiro Kasahara

IPC分类号： H01L021/8238

CPC分类号： H04L25/0272 ,  H01L2224/05554 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/3011 ,  H04L25/0278 ,  H04L25/0282 ,  H04L25/0292 ,  H01L2924/00

摘要： There are provided a semiconductor integrated device capable of achieving stable high-speed data transfer through a differential pair of signal lines and electronic equipment including the semiconductor integrated device. In a signal-transmission period in which current is driven through one of first and second signal lines forming a differential pair, current from a constant current source is caused to flow through a current path to one of a DP pad and DM pad. Current is caused to flow into a DA pad in a period other than the signal-transmission period. A layout arrangement of the current paths from a node ND to which current from the constant current source is supplied to the DP pad and the DM pad is symmetrical. The DA pad is disposed between the DP pad and the DM pad.

摘要翻译： 提供了能够通过差分信号线和包括半导体集成器件的电子设备实现稳定的高速数据传输的半导体集成器件。 在通过形成差分对的第一和第二信号线之一驱动电流的信号传输时段中，使来自恒定电流源的电流通过电流路径流过DP焊盘和DM焊盘之一。 使电流在信号传输周期以外的时段内流入DA焊盘。 来自节点ND的来自恒定电流源的电流的电流路径的布局布置被提供给DP焊盘和DM焊盘是对称的。 DA焊盘设置在DP焊盘和DM焊盘之间。

公开(公告)号：US20020056069A1

公开(公告)日：2002-05-09

申请号：US09974796

申请日：2001-10-12

申请人： SEIKO EPSON CORPORATION

发明人： Akira Abe ,  Yoshiyuki Kamihara ,  Shoichiro Kasahara

IPC分类号： G06F017/50

CPC分类号： H04L7/0337 ,  G06F1/06 ,  H03K3/0322 ,  H03L7/0996 ,  H03L7/18

摘要： A clock generation circuit capable of generating a high-frequency clock with a simple circuit configuration, together with a data transfer control device and an electronic instrument using the same. The clock generation circuit has: serially-connected inversion circuits IV0 to IV4 in which an output of IV4 is connected to an input of IV0 by a feedback line FL; and buffer circuits BF0 to BF4 which receives outputs from IV0 to IV4. The inversion circuits IV0 to IV4 are disposed along a line LN1 and the buffer circuits BF0 to BF4 are disposed along a line LN2 that is parallel to the feedback line FL but different from LN1. Dummy lines DL0 to DL3 each of which having parasitic capacitance that is equal to that of the feedback line FL are connected to the inversion circuits IV0 to IV3, to equalize the phase differences between clocks CK0 to CK4. The feedback line FL and the dummy lines DL0 to DL3 are disposed in a region between the inversion circuits IV0 to IV4 and the buffer circuits BF0 to BF4. Between which edges of multi-phase clocks an edge of data (data transferred in USB 2.0 HS mode) is located is detected, and a clock selected on the basis of edge detection information is set as a sampling clock.

摘要翻译： 一种能够以简单的电路配置产生高频时钟的时钟发生电路，以及数据传输控制装置和使用该时钟的电子仪器。 时钟发生电路具有：串行连接的反相电路IV0〜IV4，其中IV4的输出通过反馈线FL连接到IV0的输入; 以及接收从IV0至IV4的输出的缓冲电路BF0至BF4。 反相电路IV0至IV4沿线LN1布置，并且缓冲电路BF0至BF4沿着平行于反馈线FL但不同于LN1的线LN2设置。 具有与反馈线FL的寄生电容相等的寄生电容的虚线DL0〜DL3连接到反相电路IV0〜IV3，以均衡时钟CK0〜CK4之间的相位差。 反馈线FL和虚线DL0〜DL3配置在反相电路IV0〜IV4与缓冲电路BF0〜BF4之间的区域。 在多相时钟的边缘之间检测数据边缘（以USB 2.0 HS模式传输的数据），并将基于边缘检测信息选择的时钟设置为采样时钟。