公开(公告)号：US20020171577A1

公开(公告)日：2002-11-21

申请号：US10141846

申请日：2002-05-10

申请人： SEIKO EPSON CORPORATION

发明人： Shoichiro Kasahara ,  Chisato Akiyama ,  Fumikazu Komatsu

IPC分类号： H04L017/02 ,  G08C019/12

CPC分类号： G06F13/385

摘要： A macrocell MC1 including a physical-layer circuit in accordance with USB 2.0 or the like is placed at a corner of an integrated circuit device ICD. Data terminals DP and DM are placed in an I/O region IOR1 along a side SD1; and power terminals PVDD, PVSS, XVDD, and XVSS and clock terminals XI and XO of a clock generation circuit and a sampling clock circuit are placed in an I/O region IOR2 along a side SD2. An interface region and a macrocell MC2 including user-specified logic are provided along a side SD3. A reception circuit is placed on a DR1 side of IOR1, a clock generation circuit is placed on a DR2 side of IOR2, and a sampling clock generation circuit is placed on the DR1 side of the reception circuit and also the DR2 side of the clock generation circuit. A transmission circuit is placed on the DR2 side of the reception circuit and on the DR1 side of the data terminals DP and DM.

摘要翻译： 包括根据USB 2.0等的物理层电路的宏单元MC1被放置在集成电路器件ICD的角落处。 数据端子DP和DM沿着侧面SD1放置在I / O区域IOR1中; 并且时钟发生电路和采样时钟电路的电源端子PVDD，PVSS，XVDD和XVSS以及时钟端子XI和XO沿着侧面SD2放置在I / O区域IOR2中。 沿着侧面SD3提供包括用户指定逻辑的接口区域和宏单元MC2。 接收电路放置在IOR1的DR1侧，时钟发生电路放置在IOR2的DR2侧，采样时钟产生电路位于接收电路的DR1侧，时钟生成的DR2侧 电路。 传输电路放置在接收电路的DR2侧和数据端子DP和DM的DR1侧。