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    MULTI-PHASE CLOCK GENERATOR, MEMORY DEVICE INCLUDING MULTI-PHASE CLOCK GENERATOR, AND METHOD OF GENERATING MULTI-PHASE CLOCK OF MEMORY DEVICE
    1.
    发明申请
    MULTI-PHASE CLOCK GENERATOR, MEMORY DEVICE INCLUDING MULTI-PHASE CLOCK GENERATOR, AND METHOD OF GENERATING MULTI-PHASE CLOCK OF MEMORY DEVICE 有权

    公开(公告)号：US20210358534A1

    公开(公告)日：2021-11-18

    申请号：US17139538

    申请日：2020-12-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HUNDAE CHOI ,  GARAM CHOI

    IPC: G11C11/4076 ,  H03L7/081 ,  H03L7/085

    Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

    CALIBRATION CIRCUIT FOR CONTROLLING RESISTANCE OF OUTPUT DRIVER CIRCUIT, MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE
    2.
    发明申请
    CALIBRATION CIRCUIT FOR CONTROLLING RESISTANCE OF OUTPUT DRIVER CIRCUIT, MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE 有权

    公开(公告)号：US20210027827A1

    公开(公告)日：2021-01-28

    申请号：US16822164

    申请日：2020-03-18

    Applicant: SAMSUNG ELECTRONICS co., LTD.

    Inventor： HWAPYONG KIM ,  HUNDAE CHOI ,  JUNHA LEE

    IPC: G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  H03K19/00

    Abstract: A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.

    MULTI-PHASE CLOCK GENERATOR, MEMORY DEVICE INCLUDING MULTI-PHASE CLOCK GENERATOR, AND METHOD OF GENERATING MULTI-PHASE CLOCK OF MEMORY DEVICE
    3.
    发明申请
    MULTI-PHASE CLOCK GENERATOR, MEMORY DEVICE INCLUDING MULTI-PHASE CLOCK GENERATOR, AND METHOD OF GENERATING MULTI-PHASE CLOCK OF MEMORY DEVICE 有权

    公开(公告)号：US20220343965A1

    公开(公告)日：2022-10-27

    申请号：US17811503

    申请日：2022-07-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HUNDAE CHOI ,  Garam Choi

    IPC: G11C11/4076 ,  H03L7/081 ,  H03L7/085

    Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

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