公开(公告)号：US20210232521A1

公开(公告)日：2021-07-29

申请号：US16929260

申请日：2020-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Dongjoo Kim ,  Jaekuk Park ,  Yujin Oh ,  Moonki Jang ,  Jieun Jeong

IPC: G06F13/38 ,  G06F11/07 ,  G06F11/14 ,  G06F13/40 ,  B60T7/12 ,  B60R16/023 ,  H04L12/40

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

公开(公告)号：US11609874B2

公开(公告)日：2023-03-21

申请号：US17347769

申请日：2021-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Dongjoo Kim ,  Jaekuk Park ,  Yujin Oh ,  Moonki Jang ,  Jieun Jeong

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/40 ,  G06F13/38 ,  B60T7/12 ,  B60R16/023 ,  H04L12/40

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

公开(公告)号：US11074207B1

公开(公告)日：2021-07-27

申请号：US16929260

申请日：2020-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Dongjoo Kim ,  Jaekuk Park ,  Yujin Oh ,  Moonki Jang ,  Jieun Jeong

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/40 ,  G06F13/38 ,  B60T7/12 ,  H04L12/40 ,  B60R16/023

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.