公开(公告)号：US12153808B2

公开(公告)日：2024-11-26

申请号：US18148289

申请日：2022-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Moonki Jang ,  Yunhwan Kim ,  Myeongwhan Hyun

IPC: G06F3/06

Abstract: A memory device includes a row decoder that receives one or more normal addresses and one or more control addresses, and a memory cell array connected to the row decoder via a plurality of word lines. In a normal operation, in response to receiving the one or more normal addresses, any one word line among the plurality of word lines is enabled. In an initialization operation, in response to receiving the one or more normal addresses and the one or more control addresses, at least two word lines among the plurality of word lines are enabled. Data of memory cells of the memory cell array connected to the enabled at least two word lines is initialized.

公开(公告)号：US11366711B2

公开(公告)日：2022-06-21

申请号：US16774058

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Moonki Jang

IPC: G06F11/07

Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.

公开(公告)号：US20210019214A1

公开(公告)日：2021-01-21

申请号：US16774058

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Moonki Jang

IPC: G06F11/07

Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.

公开(公告)号：US11609874B2

公开(公告)日：2023-03-21

申请号：US17347769

申请日：2021-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Dongjoo Kim ,  Jaekuk Park ,  Yujin Oh ,  Moonki Jang ,  Jieun Jeong

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/40 ,  G06F13/38 ,  B60T7/12 ,  B60R16/023 ,  H04L12/40

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

公开(公告)号：US11074207B1

公开(公告)日：2021-07-27

申请号：US16929260

申请日：2020-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Dongjoo Kim ,  Jaekuk Park ,  Yujin Oh ,  Moonki Jang ,  Jieun Jeong

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/40 ,  G06F13/38 ,  B60T7/12 ,  H04L12/40 ,  B60R16/023

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

公开(公告)号：US11853147B2

公开(公告)日：2023-12-26

申请号：US17752008

申请日：2022-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Moonki Jang

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/0745 ,  G06F11/0787

Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.

公开(公告)号：US20210232521A1

公开(公告)日：2021-07-29

申请号：US16929260

申请日：2020-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Dongjoo Kim ,  Jaekuk Park ,  Yujin Oh ,  Moonki Jang ,  Jieun Jeong

IPC: G06F13/38 ,  G06F11/07 ,  G06F11/14 ,  G06F13/40 ,  B60T7/12 ,  B60R16/023 ,  H04L12/40

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.