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    MEMORY DEVICE INCLUDING ON-DIE-TERMINATION CIRCUIT
    1.
    发明申请
    MEMORY DEVICE INCLUDING ON-DIE-TERMINATION CIRCUIT 有权

    公开(公告)号：US20210201964A1

    公开(公告)日：2021-07-01

    申请号：US17182357

    申请日：2021-02-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： EUN-JI KIM ,  JUNG-JUNE PARK ,  JEONG-DON IHM ,  BYUNG-HOON JEONG ,  YOUNG-DON CHOI

    IPC: G11C7/10

    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

    MEMORY DEVICE INCLUDING ON-DIE-TERMINATION CIRCUIT
    3.
    发明申请
    MEMORY DEVICE INCLUDING ON-DIE-TERMINATION CIRCUIT 审中-公开

    公开(公告)号：US20190139585A1

    公开(公告)日：2019-05-09

    申请号：US16058709

    申请日：2018-08-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： EUN-JI KIM ,  JUNG-JUNE PARK ,  JEONG-DON IHM ,  BYUNG-HOON JEONG ,  YOUNG-DON CHOI

    IPC: G11C7/10

    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

    MEMORY DEVICE INCLUDING ON-DIE-TERMINATION CIRCUIT
    4.
    发明公开
    MEMORY DEVICE INCLUDING ON-DIE-TERMINATION CIRCUIT 审中-公开

    公开(公告)号：US20230298639A1

    公开(公告)日：2023-09-21

    申请号：US18201853

    申请日：2023-05-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： EUN-JI KIM ,  JUNG-JUNE PARK ,  JEONG-DON IHM ,  BYUNG-HOON JEONG ,  YOUNG-DON CHOI

    IPC: G11C7/10

    CPC classification number: G11C7/1048 ,  G11C7/1084 ,  G11C7/1057 ,  G11C2207/105

    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

    MEMORY DEVICE INCLUDING ON-DIE-TERMINATION CIRCUIT
    8.
    发明申请
    MEMORY DEVICE INCLUDING ON-DIE-TERMINATION CIRCUIT 审中-公开

    公开(公告)号：US20200279591A1

    公开(公告)日：2020-09-03

    申请号：US16875163

    申请日：2020-05-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： EUN-JI KIM ,  JUNG-JUNE PARK ,  JEONG-DON IHM ,  BYUNG-HOON JEONG ,  YOUNG-DON CHOI

    IPC: G11C7/10

    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

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