公开(公告)号：US20210250189A1

公开(公告)日：2021-08-12

申请号：US17014418

申请日：2020-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNGMOON AHN ,  YONGSOO KIM ,  YONGKI LEE ,  YUNHYEOK CHOI ,  BOHDAN KARPINSKYY

IPC: H04L9/32 ,  G06F21/64 ,  H04L9/08

Abstract: A security device generates a key based on a physically unclonable function (PUF). The security device includes a physically unclonable function (PUF) block, an integrity detector, and a post processor. The PUF block outputs a plurality of first random signals and a plurality of corresponding first inverted random signals each having a logic level opposite to that of each of the plurality of corresponding first random signals. The integrity detector determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals. The post processor generates a first row key that includes validity signals satisfying the data integrity.

公开(公告)号：US20230052055A1

公开(公告)日：2023-02-16

申请号：US17973252

申请日：2022-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNGMOON AHN ,  YONGSOO KIM ,  YONGKI LEE ,  YUNHYEOK CHOI ,  BOHDAN KARPINSKYY

IPC: H04L9/32 ,  H04L9/08 ,  G06F21/64

Abstract: A security device generates a key based on a physically unclonable function (PUF). The security device includes a physically unclonable function (PUF) block, an integrity detector, and a post processor. The PUF block outputs a plurality of first random signals and a plurality of corresponding first inverted random signals each having a logic level opposite to that of each of the plurality of corresponding first random signals. The integrity detector determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals. The post processor generates a first row key that includes validity signals satisfying the data integrity.

公开(公告)号：US20220385297A1

公开(公告)日：2022-12-01

申请号：US17827135

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGNO LEE ,  HEECHANG HWANG ,  YONGKI LEE ,  KYOUNGJUN MOON ,  HYOCHUL SHIN ,  MICHAEL CHOI

IPC: H03M1/10

Abstract: An analog-to-digital conversion circuit includes analog-to-digital converters (ADCs) including a target analog-to-digital converter (ADC) providing second data samples, a first adjacent ADC providing first data samples, and a second adjacent ADC providing third data samples. The ADCs perform an analog-to-digital conversion using a time-interleaving approach in response to clock signals having different phases and including a reference clock signal. A timing calibration circuit includes a relative time skew generator generating a relative time skew and an absolute time skew generator generate an absolute time skew. A clock generator adjusts at least one phase of the clock signals based on the absolute time skew.