公开(公告)号：US20220037328A1

公开(公告)日：2022-02-03

申请号：US17210931

申请日：2021-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyewon KIM ,  Juhyung WE ,  Sungmi YOON ,  Donghyun IM ,  Sangwoon LEE ,  Taiuk RIM ,  Kyosuk CHAE

IPC: H01L27/108

Abstract: A semiconductor device including a substrate including a recess; a gate insulation layer on a surface of the recess; a first gate pattern on the gate insulation layer and filling a lower portion of the recess; a second gate pattern on the first gate pattern in the recess and including a material having a work function different from a work function of the first gate pattern; a capping insulation pattern on the second gate pattern and filling an upper portion of the recess; a leakage blocking oxide layer on the gate insulation layer at an upper sidewall of the recess above an upper surface of the first gate pattern and contacting a sidewall of the capping insulation pattern; and impurity regions in the substrate and adjacent to the upper sidewall of the recess, each impurity region having a lower surface higher than the upper surface of the first gate pattern.

公开(公告)号：US20240244835A1

公开(公告)日：2024-07-18

申请号：US18517325

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taiuk RIM ,  Jinseong LEE ,  Kyosuk CHAE

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral circuit region, a first gate structure in the cell region of the substrate, the first gate structure extending in a first direction parallel to an upper surface of the substrate, bit line structures on the cell region of the substrate, the bit line structures extending in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate, a second gate structure on the peripheral circuit region of the substrate, contact plug structures between the bit line structures, the contact plug structures contacting the substrate, first conductive structures on peripheral circuit region of the substrate, the first conductive structures being electrically connected to the peripheral circuit region of the substrate, a first upper insulation structure between the first conductive structures, the first upper insulation structure including a first upper insulation pattern and a hydrogen diffusing insulation pattern surrounding a bottom and sidewalls of the first upper insulation pattern, and a second upper insulation pattern between upper portions of the contact plug structures.

公开(公告)号：US20230225113A1

公开(公告)日：2023-07-13

申请号：US17959634

申请日：2022-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon NA ,  Sungsam LEE ,  Taiuk RIM ,  Byungha KANG ,  Kanghyun KIM

IPC: H01L27/108

CPC classification number: H01L27/10814

Abstract: A semiconductor device includes a substrate including first and second active regions; a bitline structure extending in one direction on the substrate, the bitline structure being electrically connected to the first active region; a storage node contact on a sidewall of the bitline structure, the storage node contact being electrically connected to the second active region; a spacer structure between the bitline structure and the storage node contact; a landing pad on the storage node contact, the landing pad being in contact with a sidewall of the spacer structure; and a capacitor structure electrically connected to the landing pad, wherein the spacer structure includes a first spacer, a second spacer, a third spacer, and a fourth spacer, sequentially stacked on the sidewall of the bitline structure, the second spacer is an air spacer, and the third spacer has a thickness that is less than a thickness of the first spacer.