Electronic device including coin-cell battery

    公开(公告)号:US12144123B2

    公开(公告)日:2024-11-12

    申请号:US17957697

    申请日:2022-09-30

    Abstract: An electronic device including a coin-cell battery is provided. The electronic device further includes a housing, a battery comprising a first surface, a second surface, and a third surface, a first electrode disposed in the first surface and a second electrode disposed in the second surface, a first electrode tap, a second electrode tap, and a printed circuit board connecting the first electrode tap to the second electrode tap of the battery on the third surface. Soldering parts are formed on a first surface of the printed circuit board to connect an end of the first electrode tap to a first contact portion of the printed circuit board and an end of the second electrode tap to a second contact portion of the printed circuit board, respectively. A solder flow control member is formed on a second surface of the printed circuit board.

    Method for keyless reset, and electronic device therefor

    公开(公告)号:US11755086B2

    公开(公告)日:2023-09-12

    申请号:US17483423

    申请日:2021-09-23

    CPC classification number: G06F1/24 G06F1/163 G06F1/263 G06F1/3228

    Abstract: Disclosed is an electronic device comprising: a connection circuit configured to provide an electrical connection of an external power supply device; a processor electrically connected to the connection circuit; a memory operatively connected to the processor; and a reset circuit electrically connected to the connection circuit and operatively connected to the processor. The processor is configured to” transmit, to the reset circuit, an interrupt signal during a first time at least partially based on the identification of the connecting to the external power supply device through the connection circuit, and the reset circuit may be configured to: determine whether the interrupt signal is received within a second time after the connecting to the external power supply device through the connection circuit, and transmit, to the processor, a reset signal for a hardware reset of the processor based on the interrupt signal not being received within the second time.

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