公开(公告)号：US20240211177A1

公开(公告)日：2024-06-27

申请号：US18345492

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonik SEO ,  Dong-Uk RYU ,  Sungduk CHO

IPC: G06F3/06

CPC classification number: G06F3/0665 ,  G06F3/0604 ,  G06F3/0673

Abstract: A method including updating memory allocation information of a UVM based on block information of model data blocks used for an execution of a deep learning model by a deep learning framework, and performing a least recently used (LRU) eviction based on the updated memory allocation information.

公开(公告)号：US20230251780A1

公开(公告)日：2023-08-10

申请号：US18089839

申请日：2022-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungduk CHO ,  Ruth KIM ,  Dong-Uk RYU ,  Jaewon LEE

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0683

Abstract: An apparatus includes a memory configured to store data, and a processor. The processor configured to determine whether an access to the data is a local memory access; determine, based on a result of the determination of whether the access to the data is the local memory access, whether a page fault of the access occurred; determine, based on a result of the determination of whether the page fault occurred, whether the access is a remote access outside a socket; and perform, based on a result of the determination of whether the access is the remote access, the access to the data by copying the data onto a local memory.

公开(公告)号：US20220171658A1

公开(公告)日：2022-06-02

申请号：US17327600

申请日：2021-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jieun LEE ,  Jin-Hong KIM ,  Jaehyung AHN ,  Sungduk CHO

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/54

Abstract: An active scheduling method performed with a master processor and a plurality of slave processors. The method includes determining whether a job to be performed has a dependency by referencing a job queue; in a case in which it is determined that the job to be performed has a dependency, updating a state of the job to be performed in a table in which information of each of a plurality of jobs is recorded; analyzing a state of a job preceding the job to be performed based on the table; and in a case in which the job preceding the job to be performed is determined to have been completed, performing the job to be performed by retrieving the job to be performed from the job queue.

公开(公告)号：US20250094346A1

公开(公告)日：2025-03-20

申请号：US18964849

申请日：2024-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonik SEO ,  Dong-uk RYU ,  Sungduk CHO

IPC: G06F12/08

Abstract: A method and apparatus for managing a unified virtual memory (UVM) are provided. The UVM is backed by a main processor memory and a coprocessor memory, and the method includes: checking properties of data blocks of the UVM used to execute a deep learning model; based on a first of the data blocks storing weight data of the deep learning model, storing the first data block in the main processor memory among the main processor memory and the coprocessor memory; and performing an operation of the deep learning model based on the first data block using a coprocessor while directly loading at least a portion of the first data block from the main processor memory into a cache memory of the coprocessor without migration of the first data block from the main processor memory to the coprocessor memory.

公开(公告)号：US20240220407A1

公开(公告)日：2024-07-04

申请号：US18343099

申请日：2023-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonik SEO ,  Dong-uk RYU ,  Sungduk CHO

IPC: G06F12/08 ,  G06N3/0455 ,  G06N3/084

CPC classification number: G06F12/08 ,  G06N3/0455 ,  G06N3/084

Abstract: A method and apparatus for managing a unified virtual memory (UVM) are provided. The UVM is backed by a main processor memory and a coprocessor memory, and the method includes: checking properties of data blocks of the UVM used to execute a deep learning model; based on a first of the data blocks storing weight data of the deep learning model, storing the first data block in the main processor memory among the main processor memory and the coprocessor memory; and performing an operation of the deep learning model based on the first data block using a coprocessor while directly loading at least a portion of the first data block from the main processor memory into a cache memory of the coprocessor without migration of the first data block from the main processor memory to the coprocessor memory.