公开(公告)号：US12038458B2

公开(公告)日：2024-07-16

申请号：US17524841

申请日：2021-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Hoon Lee ,  Gyuyeol Kim ,  Yu-Kyum Kim ,  Hanjik Nam ,  Sehoon Park ,  Young Jun Park ,  Seungwon Jeong ,  Woojun Choi

IPC: G01R1/073 ,  G01R1/04 ,  G01R1/067

CPC classification number: G01R1/07342 ,  G01R1/06727

Abstract: A probe for testing a semiconductor device includes a post having a plate shape and connected to a test substrate. A beam has a first end connected to the post. A tip structure is connected to a second end of the beam. The post includes a front surface having a normal line extending in a first direction. A back surface is located opposite to the front surface. Bumps are disposed on the front surface and are spaced apart from each other. The beam extends in a second direction intersecting the first direction. Each of the bumps protrudes from the front surface in the first direction by a first length.

公开(公告)号：US20250149107A1

公开(公告)日：2025-05-08

申请号：US18669872

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehoon Park ,  Hyounsoon Km ,  Donggun Kim ,  Joonyeon Kim ,  Hyungsoon Kim

IPC: G11C29/56 ,  G01R31/317 ,  G01R31/319

Abstract: A test device includes a plurality of input/output terminals configured to be electrically connected to the devices formed on the wafer, a comparative circuit configured to receive a plurality of test signals from a device under test formed on the wafer, and generate a plurality of test result signals, based on the plurality of test signals, and a memory configured to receive the plurality of test result signals and store bad cell information and repair information related to the device under test, which are indicated by the plurality of test result signals, wherein the total number of the plurality of test signals received from the device under test at one time is an integer.

公开(公告)号：US11585833B2

公开(公告)日：2023-02-21

申请号：US17498820

申请日：2021-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehoon Park

IPC: G01R31/28 ,  G01R1/073

Abstract: A probe card includes a sub-board, having a heating layer, connected to a probe pin. A main board is connected to the sub-board and includes a first output terminal configured to output first power received from a first power supply to the heating layer in a first mode. A power converter is configured to lower a first voltage corresponding to residual power received from the first power supply to a second voltage and output the residual power in a second mode. A second output terminal is configured to receive the residual power from the power converter and second power from a second power supply and output third power including the residual power and the second power to a device under test in the second mode. A first switch unit is connected to the first power supply, the first output terminal, and the power converter.