公开(公告)号：US20250149107A1

公开(公告)日：2025-05-08

申请号：US18669872

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehoon Park ,  Hyounsoon Km ,  Donggun Kim ,  Joonyeon Kim ,  Hyungsoon Kim

IPC: G11C29/56 ,  G01R31/317 ,  G01R31/319

Abstract: A test device includes a plurality of input/output terminals configured to be electrically connected to the devices formed on the wafer, a comparative circuit configured to receive a plurality of test signals from a device under test formed on the wafer, and generate a plurality of test result signals, based on the plurality of test signals, and a memory configured to receive the plurality of test result signals and store bad cell information and repair information related to the device under test, which are indicated by the plurality of test result signals, wherein the total number of the plurality of test signals received from the device under test at one time is an integer.