公开(公告)号：US20230019860A1

公开(公告)日：2023-01-19

申请号：US17718703

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Dong KO ,  Keon Yong CHEON ,  Dong Won KIM ,  Hyun Suk KIM ,  Sang Hyeon LEE ,  Hyung Suk LEE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L21/8234

Abstract: A semiconductor device including a substrate; first and second active patterns on the substrate, extending in a first direction and spaced apart in a second direction; gate electrodes on the first and second active patterns and extending in the second direction; a first gate separation structure between the first and second active patterns, extending in the first direction, and separating the gate electrodes; and a first element separation structure between the gate electrodes, extending in the second direction, and separating the second active pattern, wherein a distance to a first side of a first portion of the first gate separation structure is smaller than a distance to the first side of a second portion of the first gate separation structure, and a distance to the second side of the first portion is smaller than a distance from the second active pattern to the second side of the second portion.

公开(公告)号：US20230122379A1

公开(公告)日：2023-04-20

申请号：US17879134

申请日：2022-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin Cheol MIN ,  Keon Yong CHEON ,  Myung Dong KO ,  Yong Hee PARK ,  Sang Hyeon LEE ,  Dong Won KIM ,  Woo Seung SHIN ,  Hyung Suk LEE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern, a gate structure on the lower pattern and having a gate electrode and a gate insulating film that surround each of the sheet patterns, a gate capping pattern on the gate structure, a gate etching stop pattern between the gate capping pattern and the gate structure, a gate spacer along a sidewall of the gate capping pattern, a source/drain pattern on the gate structure, a gate contact through the gate capping pattern and connected to the gate electrode, upper surfaces of the gate contact and gate spacer being coplanar, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern.