公开(公告)号：US20240113057A1

公开(公告)日：2024-04-04

申请号：US18231102

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUHYEON KIM ,  YEONGSEON KIM ,  SUNKYOUNG SEO ,  CHAJEA JO

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L23/5383 ,  H01L24/05 ,  H01L2224/05556 ,  H01L2224/08145

Abstract: A semiconductor package includes a first semiconductor chip stacked on a second semiconductor chip. The first semiconductor chip includes a first substrate, a first insulating layer on a lower surface of the first substrate, and a first pad exposed through the first insulating layer. The second semiconductor chip includes a second substrate, a second insulating layer on an upper surface of the second substrate contacting the first insulating layer, and a second pad exposed through the second insulating layer contacting the first pad. The first pad has an inclined side surface and a first width that increases toward the first substrate, and the second pad has an inclined side surface and a second width that increases toward the second substrate.

公开(公告)号：US20210398929A1

公开(公告)日：2021-12-23

申请号：US17165429

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOEUN KIM ,  SUNKYOUNG SEO ,  SEUNGHOON YEON ,  CHAJEA JO

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.

公开(公告)号：US20220122955A1

公开(公告)日：2022-04-21

申请号：US17357378

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGHOE CHO ,  SUNKYOUNG SEO ,  CHAJEA JO

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/538 ,  H01L23/14 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, a connection substrate on the package substrate, a first image sensor chip on the connection substrate, a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip, and a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate. A distance between the first image sensor chip and the second image sensor chip is less than a thickness of the first image sensor chip.

公开(公告)号：US20250105127A1

公开(公告)日：2025-03-27

申请号：US18659864

申请日：2024-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyun KIM ,  Yeongseon KIM ,  JUHYEON KIM ,  HYOEUN KIM ,  SUNKYOUNG SEO ,  Haksun LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/544 ,  H01L25/10

Abstract: A semiconductor package may include a first dielectric structure, a first pad in the first dielectric structure, a first semiconductor chip provided on the first dielectric structure, and a bump electrically connected to the first pad. The first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad. The first pad may be provided between the bump and the first chip of the first semiconductor chip. The first pad may include a first conductive layer and a second conductive layer covered by the first conductive layer. The bump may be positioned closer to the first conductive layer than to the second conductive layer.

公开(公告)号：US20210167040A1

公开(公告)日：2021-06-03

申请号：US16906051

申请日：2020-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： SE-HO YOU ,  KYUNG SUK OH ,  SUNKYOUNG SEO

IPC: H01L25/065 ,  H01L25/18 ,  H01L21/78 ,  H01L25/00

Abstract: Disclosed is a semiconductor package comprising a first memory chip including a first semiconductor substrate and a first through structure that penetrates the first semiconductor substrate, a second memory chip that directly contacts a top surface of the first memory chip and includes a second semiconductor substrate and a second through structure that penetrates the second semiconductor substrate, a first dummy chip that directly contacts a top surface of the second memory chip and includes a first conductive via, a second dummy chip that directly contacts a top surface of the first dummy chip and includes a second conductive via, and a logic chip in direct contact with a top surface of the second dummy chip. The logic chip is electrically connected to the first through structure through the second conductive via, the first conductive via, and the second through structure.