公开(公告)号：US20240072802A1

公开(公告)日：2024-02-29

申请号：US18349823

申请日：2023-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOUNGJOONG KIM ,  CHEOLMIN AHN ,  MYEONG-CHEOL KIM ,  WOONGKI MIN ,  SANGHO KIM ,  SOOMIN LEE

IPC: H03K19/003

CPC classification number: H03K19/00315

Abstract: A electronic device includes a transceiver including a transmitter and a receiver that operate based on a power source voltage and a pad voltage applied from a pad; and an overvoltage protection circuit to apply a first protection voltage to the transmitter and a second protection voltage to the receiver. The overvoltage protection circuit includes: a reference voltage generator to generate a reference voltage when the power source voltage is in an on state; and a voltage detector to set the first protection voltage and the second protection voltage based on the reference voltage when the power source voltage is in an on state, and set the first protection voltage and the second protection voltage based on the pad voltage when the power source voltage is in an off state.

公开(公告)号：US20200243129A1

公开(公告)日：2020-07-30

申请号：US16543765

申请日：2019-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOOMIN LEE

IPC: G11C11/4096 ,  H04L1/00 ,  H04L25/03

Abstract: An electronic circuit including: a driver for outputting a driven first signal by driving a first signal among signals received in parallel; a selector circuit for selecting one of the first signal and a second signal among the signals received in parallel; and a compensator circuit for generating a first compensation signal for compensating the driven first signal, in response to the first signal or the second signal selected by the selector circuit, wherein, when the selector circuit selects the first signal, the compensator circuit generates the first compensation signal to compensate for an inter-symbol interference of the driven first signal, and wherein, when the selector circuit selects the second signal, the compensator circuit generates the first compensation signal to compensate for a crosstalk noise of the driven first signal caused by a driven second signal driven from the second signal.

公开(公告)号：US20240088922A1

公开(公告)日：2024-03-14

申请号：US18241963

申请日：2023-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HORANG JANG ,  BEOMWOO LEE ,  SOOMIN LEE

IPC: H04B1/00 ,  H03F3/45

CPC classification number: H04B1/0078 ,  H03F3/45071

Abstract: A communication device includes a first device and a second device. The first device includes a transmitting circuit configured to output and transmit a differential signal including a first signal and a second signal to the second device using an input signal and an enable signal. The second device includes a first amplifier configured to receive the differential signal from the first device, a gate circuit configured to gate an output signal of the first amplifier based on a deactivated reset signal, and a count circuit configured to: (1) count a section in which a value of the differential signal is constant based on a clock signal and an output signal of the gate circuit and (2) generate an activated reset signal when the count of the section exceeds a threshold value.

公开(公告)号：US20250070914A1

公开(公告)日：2025-02-27

申请号：US18788699

申请日：2024-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN MIN ,  JAHOON JIN ,  SANGHO KIM ,  JISU YOOK ,  SOOMIN LEE ,  JIHOON LEE

IPC: H04L1/00 ,  H04L25/03

Abstract: Disclosed are a transmitter and transceiver for improving switching jitter. The transmitter includes an encoder that encodes an input signal representable by x levels (where x is a natural number of 3 or more) and outputs a plurality of encoded signals representing a multi-bit binary number including a most significant bit and a least significant bit; an edge adjustment circuit that generates a plurality of adjusted encoded signals by adjusting a falling edge timing of a first one of the encoded signals corresponding to the most significant bit and adjusting a rising edge timing of a second one of the encoded signals corresponding to the least significant bit; and a driver circuit that generates and outputs an output signal having the x levels based on the adjusted encoded signals.