公开(公告)号：US10546093B2

公开(公告)日：2020-01-28

申请号：US15867470

申请日：2018-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon-Su Kim

IPC: G06F17/50 ,  G03F1/70 ,  G03F1/36

Abstract: A computer-implemented method and a computing system for designing an integrated circuit are provided. The computer-implemented method of designing an integrated circuit includes receiving layout data for the integrated circuit and a technology file that includes corners of a parasitic component of each of a plurality of layers included in the integrated circuit, generating parasitic component data by performing a parasitic component extraction operation on corners of a parasitic component of a layer in a timing arc on a net of the integrated circuit, the parasitic component data including delay variation data of the timing arc, and generating timing analysis data by performing a timing analysis on the integrated circuit, based on the parasitic component data.

公开(公告)号：US10372869B2

公开(公告)日：2019-08-06

申请号：US15081291

申请日：2016-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon-Su Kim ,  Naya Ha ,  Jong-Ku Kang ,  Andrew Paul Hoover

IPC: G06F17/50

Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

公开(公告)号：US10192015B2

公开(公告)日：2019-01-29

申请号：US15096508

申请日：2016-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon-Su Kim ,  Kyoung-Hwan Lim ,  Cheol-Jun Bae

IPC: G06F17/50 ,  G06F9/455

Abstract: Methods of estimating yields of integrated circuits and methods of optimizing designs for the integrated circuits are provided. In a method of estimating a yield of an integrated circuit, critical paths are extracted from timing paths included in the integrated circuit by performing a static timing analysis for the integrated circuit. The critical paths are grouped into criticality sigma level groups according to criticality sigma levels of the critical paths, and the yield of the integrated circuit is determined based on numbers of the critical paths belonging to the respective criticality sigma level groups.

公开(公告)号：US09977845B2

公开(公告)日：2018-05-22

申请号：US14982921

申请日：2015-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Moon-Su Kim

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5022 ,  G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

Abstract: A method of performing a static timing analysis on an integrated circuit includes loading a library that includes local random variation information of the integrated circuit and global variation information of the integrated circuit that is obtained based on a set of a plurality of global variation parameters of the integrated circuit, calculating delays of timing arcs included in the integrated circuit based on the library, and determining whether at least one timing path of a plurality of timing paths included in the integrated circuit violates a timing constraint based on the delays of the timing arcs in the at least one timing path, the local random variation information of the integrated circuit and the global variation information of the integrated circuit.

公开(公告)号：US11256846B2

公开(公告)日：2022-02-22

申请号：US16404910

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon-Su Kim ,  Naya Ha ,  Jong-Ku Kang ,  Andrew Paul Hoover

IPC: G06F30/398 ,  G06F30/327 ,  G06F119/12

Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

公开(公告)号：US20160283643A1

公开(公告)日：2016-09-29

申请号：US15081291

申请日：2016-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon-Su Kim ,  Naya Ha ,  Jong-Ku Kang ,  Andrew Paul Hoover

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/82 ,  G06F2217/84

Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

Abstract translation: 一种分析由计算系统或处理器实现的集成电路的方法，其中集成电路的第一网络的互连包括对应于一个布线层或一个通孔的至少一个导电段，包括接收多个 基于处理变化，对应于第一网的电阻和多个电容，对与第一网相对应的导电段的数量进行计数，以及基于第一网的数量计算第一网的第一电阻或第一电容 的导电段，多个电阻和多个电容。