公开(公告)号：US10910266B2

公开(公告)日：2021-02-02

申请号：US16295751

申请日：2019-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L27/30 ,  H01L27/146 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

公开(公告)号：US11361995B2

公开(公告)日：2022-06-14

申请号：US17146597

申请日：2021-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L21/321 ,  H01L27/146 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L27/30

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

公开(公告)号：US20210166976A1

公开(公告)日：2021-06-03

申请号：US17146597

申请日：2021-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L27/30 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.