公开(公告)号：US20250167112A1

公开(公告)日：2025-05-22

申请号：US18745755

申请日：2024-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungwon Choe ,  Changbum Kim ,  Sunghoon Kim

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: An example memory device includes a lower interconnection structure on a substrate, a cell stack structure on the lower interconnection structure, an interlayer insulating layer covering the cell stack structure, an upper interconnection structure on the interlayer insulating layer, one or more effective contact structures respectively passing through the interlayer insulating layer, and one or more preliminary contact structures respectively passing through the interlayer insulating layer. The lower interconnection structure includes circuit components and lower conductive patterns. The cell stack structure includes gate electrodes stacked and spaced apart from each other in a vertical direction. The vertical direction is perpendicular to an upper surface of the substrate. The upper interconnection structure includes upper conductive patterns and one or more external pads. The one or more preliminary contact structures are electrically floating.