公开(公告)号：US11699643B2

公开(公告)日：2023-07-11

申请号：US17162015

申请日：2021-01-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ik Jun Choi ,  Jae Ean Lee ,  Kwang Ok Jeong ,  Young Gwan Ko ,  Jung Soo Byun

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/528 ,  H01L21/48 ,  H01L23/522 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/49822 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5226 ,  H01L24/18 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor package includes disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate, forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate, embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole, forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure, and forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.

公开(公告)号：US11189552B2

公开(公告)日：2021-11-30

申请号：US16867004

申请日：2020-05-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jae Ean Lee ,  Tae Sung Jeong ,  Young Gwan Ko ,  Suk Ho Lee ,  Jung Soo Byun

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00

摘要： A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.

公开(公告)号：US10446478B2

公开(公告)日：2019-10-15

申请号：US15976387

申请日：2018-05-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kwang Ok Jeong ,  Dong Won Kang ,  Young Gwan Ko ,  Ik Jun Choi ,  Jung Soo Byun

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L25/18 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

摘要： A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an underbump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member, wherein the UBM layer includes a UBM pad embedded in the passivation layer, at least one plating layer disposed on the UBM pad and having side surfaces of which at least portions are covered by the UBM pad, and a UBM via penetrating through at least portions of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.

公开(公告)号：US10796997B2

公开(公告)日：2020-10-06

申请号：US16205164

申请日：2018-11-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jae Ean Lee ,  Han Na Jin ,  Tae Sung Jeong ,  Young Gwan Ko ,  Jung Soo Byun

IPC分类号： H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18

摘要： A semiconductor package including an organic interposer includes: a semiconductor chip; a connection member on the semiconductor chip and including a pad layer, a redistribution layer, and an insulating layer; a bonding member between the semiconductor chip and the pad layer; a surface treatment layer on the pad layer and including at least one metal layer; and an under-bump metallurgy (UBM) layer embedded in the connection member. The UBM layer includes a UBM pad, at least one plating layer on the UBM pad, and a UBM via. The surface treatment layer is disposed only on one surface of the pad layer, the plating layer are is disposed only on one surface of the UBM pad, and at least a portion of a side surface of the plating layer is spaced apart from a side surface of the insulating layer surrounding the plating layer.

公开(公告)号：US10790224B2

公开(公告)日：2020-09-29

申请号：US16399540

申请日：2019-04-30

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jae Ean Lee ,  Tae Sung Jeong ,  Young Gwan Ko ,  Ik Jun Choi ,  Jung Soo Byun

IPC分类号： H01L21/00 ,  H01L23/498 ,  H01L23/15 ,  H01L21/56 ,  H01L23/532 ,  H01L21/78

摘要： A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.

公开(公告)号：US10665535B2

公开(公告)日：2020-05-26

申请号：US15913429

申请日：2018-03-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jae Ean Lee ,  Tae Sung Jeong ,  Young Gwan Ko ,  Suk Ho Lee ,  Jung Soo Byun

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00

摘要： A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.

公开(公告)号：US10438884B2

公开(公告)日：2019-10-08

申请号：US15919507

申请日：2018-03-13

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jae Ean Lee ,  Tae Sung Jeong ,  Young Gwan Ko ,  Ik Jun Choi ,  Jung Soo Byun

IPC分类号： H01L21/00 ,  H01L23/498 ,  H01L23/15 ,  H01L21/56 ,  H01L23/532 ,  H01L21/78

摘要： A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.

公开(公告)号：US10916495B2

公开(公告)日：2021-02-09

申请号：US15935526

申请日：2018-03-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ik Jun Choi ,  Jae Ean Lee ,  Kwang Ok Jeong ,  Young Gwan Ko ,  Jung Soo Byun

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/528 ,  H01L21/48 ,  H01L23/522 ,  H01L21/56 ,  H01L23/00

摘要： A semiconductor package includes a supporting member that has a cavity and includes a wiring structure connecting first and second surfaces opposing each other. A connection member is on the second surface of the supporting member and includes a first redistribution layer connected to the wiring structure. A semiconductor chip is on the connection member in the cavity and has connection pads connected to the first redistribution layer. An encapsulant encapsulates the semiconductor chip disposed in the cavity and covers the first surface of the supporting member. A second redistribution layer includes wiring patterns embedded in the encapsulant and has exposed surfaces and connection vias that penetrate through the encapsulant to connect the wiring structure and the wiring patterns to each other.