公开(公告)号：US20190214989A1

公开(公告)日：2019-07-11

申请号：US16107424

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo Seok SHON ,  Sang Woo KIM ,  Byung Tak LEE ,  Yun Ju KWON ,  Joon-Woo CHO

IPC: H03K19/00 ,  G06F1/06 ,  G06F1/32

Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a hardware auto clock gating (HWACG) logic configured to provide clock gating of an intellectual property (IP) block; and a memory power controller configured to perform power gating of a memory electrically connected with the IP block, based on the HWACG logic providing the clock gating for the IP block. The HWACG logic includes a first clock source configured to provide a first clock signal; a second clock source configured to receive the first clock signal provided by the first clock source, and provide a second clock signal to the IP block; a first clock control circuit configured to control the first clock source; and a second clock control circuit configured to transmit a clock request to the first clock control circuit, and control the second clock source, based on an operation state of the IP block.

公开(公告)号：US20140201407A1

公开(公告)日：2014-07-17

申请号：US14217536

申请日：2014-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Woo CHO ,  Jong Ho ROH ,  Jae Geun YUN ,  Sung-Min HONG

IPC: G06F13/368

CPC classification number: G06F13/368 ,  G06F12/0607 ,  G06F13/4022

Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

Abstract translation: 提供互连，具有互连的总线系统和总线系统操作方法。 总线系统包括主站，主站的从站访问和互连。 响应于由主机提供的主地址中标识的选择位，互连将主机与从机连接。