SEMICONDUCTOR DEVICE
    1.
    发明申请

    公开(公告)号:US20220084952A1

    公开(公告)日:2022-03-17

    申请号:US17379000

    申请日:2021-07-19

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20240306370A1

    公开(公告)日:2024-09-12

    申请号:US18537912

    申请日:2023-12-13

    CPC classification number: H10B12/34 H10B12/053 H10B12/315

    Abstract: A semiconductor memory device includes a substrate having an element separation film defining active areas; and gate structures in trenches on the substrate and intersecting the active areas, wherein each of the gate structures includes a gate insulating layer extending along sidewalls and a bottom surface of a corresponding one of the trenches, a gate electrode layer on the gate insulating layer and including a first metal layer and a second metal layer on the first metal layer, a liner film between the gate insulating layer and the first metal layer and including a same metal material as the first and second metal layers, and a capping film in contact with the second metal layer.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

    公开(公告)号:US20230035899A1

    公开(公告)日:2023-02-02

    申请号:US17733051

    申请日:2022-04-29

    Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

    公开(公告)号:US20250071970A1

    公开(公告)日:2025-02-27

    申请号:US18942899

    申请日:2024-11-11

    Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF

    公开(公告)号:US20220013467A1

    公开(公告)日:2022-01-13

    申请号:US17358752

    申请日:2021-06-25

    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.

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