公开(公告)号：US20240387654A1

公开(公告)日：2024-11-21

申请号：US18501354

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOONGWON JEON ,  KIHEUNG PARK ,  JAE HYUN KANG ,  BYUNG-MOO KIM

IPC: H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor devices. One example semiconductor device comprises a substrate that includes a first active pattern, a first source/drain pattern, a second source/drain pattern, and a third source/drain pattern on the first active patter, a first separation structure between the first source/drain pattern and the second source/drain pattern, and a second separation structure between the second source/drain pattern and the third source/drain pattern. The first active pattern includes a first active portion that overlaps the first source/drain pattern, a second active portion that overlaps the second source/drain pattern, a third active portion that overlaps the third source/drain pattern, a first intervening portion between the first active portion and the second active portion, and a second intervening portion between the second active portion and the third active portion.

公开(公告)号：US20240054276A1

公开(公告)日：2024-02-15

申请号：US18341142

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUBIN KIM ,  JUNSU JEON ,  JAEHYUN KANG ,  BYUNGMOO KIM ,  JOONGWON JEON

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: A method of manufacturing a semiconductor device includes designing a semiconductor device layout using a design rule manual (DRM), in which design rules are recorded, and performing failure evaluation of a failure including at least one gate structure failure of a semiconductor device manufactured using the designed semiconductor device layout. The method further includes updating the DRM by updating the design rules recorded in the DRM, based on a result of the failure evaluation, redesigning the semiconductor device layout using the updated DRM, and manufacturing the semiconductor device using the redesigned semiconductor device layout.