公开(公告)号：US20240202410A1

公开(公告)日：2024-06-20

申请号：US18510092

申请日：2023-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungil WOO ,  Joonyoung CHANG

IPC: G06F30/333 ,  G06F21/72 ,  G06F30/327

CPC classification number: G06F30/333 ,  G06F21/72 ,  G06F30/327 ,  G06F2115/08

Abstract: Disclosed is an integrated circuit including intellectual property (IP) pieces including test logics, respectively, a scanner configured to collect debugging data from the test logics of the IP pieces, and an encryption circuit configured to convert the debugging data into an encrypted data form.

公开(公告)号：US20230096746A1

公开(公告)日：2023-03-30

申请号：US17849945

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungil WOO ,  Sungcheol PARK ,  Jehyun PARK

IPC: G01R31/317 ,  G01R31/3185

Abstract: A semiconductor integrated circuit to receive a test scan input, a test clock, and a test mode signal and output a secure scan output signal, the integrated circuit including: a secure key circuit to generate delay input signals, which are differently delayed from the test scan input, and to generate an input key signal by capturing the delay input signals in response to the test clock; a key comparator to generate a verification result indicating whether an input key of the input key signal is identical with a preset reference key; a chip to generate a scan output signal based on the test scan input; a scan output remapper to obfuscate the scan output signal according to the verification result and to output the obfuscated scan output signal as the secure scan output signal; and a secure scan controller to control the secure key circuit, key comparator, chip, and remapper.