PASSIVATION SURFACE TREATMENT OF STAINLESS STEEL

    公开(公告)号:US20190203371A1

    公开(公告)日:2019-07-04

    申请号:US15984853

    申请日:2018-05-21

    CPC classification number: C25D5/36 C25D5/50 C25D11/38 C25F1/06

    Abstract: A passivation surface treatment method of stainless steel that improves corrosion resistance including in a brine environment without changing the appearance of the surface of stainless steel. A passivation surface treatment method for stainless steel includes: performing degreasing of stainless steel, performing electrolytic pickling where the stainless steel that underwent the degreasing is immersed in a pickling solution having phosphoric acid (H3PO4) and is connected to the anode and a voltage of about 0.5 to 5.0 V for about 10 seconds or more is applied, performing electrolytic degreasing of the stainless steel, and performing electrolytic passivation where the stainless steel that underwent the electrolytic degreasing is immersed in a passivation solution including dichromic acid and chromium sulfate and a voltage of about 0.5 to 5.0 V is applied for 5 seconds or more.

    VOLTAGE REGULATOR FOR SUPPRESSING OVERSHOOT AND UNDERSHOOT AND DEVICES INCLUDING THE SAME

    公开(公告)号:US20170199537A1

    公开(公告)日:2017-07-13

    申请号:US15230849

    申请日:2016-08-08

    CPC classification number: G05F1/575

    Abstract: A voltage regulator may include an error amplifier configured to amplify a difference between a reference voltage and a feedback voltage and generate a first amplified voltage based thereon; a power transistor between a second voltage supply node and an output node of the voltage regulator, the power transistor including a gate configured to receive a gate voltage; a buffer between a first voltage supply node and a ground, the buffer configured to generate the gate voltage based on the first amplified voltage; a voltage divider between the output node and the ground, the voltage divider configured to generate the feedback voltage based on the output voltage; and a control circuit configured to connect the output node to the ground through the gate of the power transistor based on the output voltage and the gate voltage.

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