公开(公告)号：US20250146130A1

公开(公告)日：2025-05-08

申请号：US18647721

申请日：2024-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongho SHIN ,  Hanhim KANG ,  Seungjae KIM ,  Oh-Hyuk KWON ,  Jaeho PARK ,  Hongtaek LIM ,  Eun-Kyung HONG

IPC: C23C16/455

Abstract: Substrate processing apparatuses and methods are provided. A substrate processing apparatus includes placing a first substrate on a first stage in a process chamber, placing a second substrate on a second stage in the process chamber, performing a first deposition process on the first substrate, and performing a second deposition process on the second substrate. The performing the first deposition process includes supplying the first substrate with a first gas. The performing the second deposition process includes supplying the second substrate with a second gas. The supplying the first substrate with the first gas includes alternately and repeatedly performing steps of filling a first gas supply unit with the first gas for a first time length, and supplying the first substrate with the first gas for a second time length. The second time length is greater than the first time length.

公开(公告)号：US20250120081A1

公开(公告)日：2025-04-10

申请号：US18761611

申请日：2024-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjun AHN ,  Hanhim KANG ,  Donghwan LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes: a mold structure; and a first high aspect ratio via disposed in a second via hole which passes through at least a portion of the mold structure, wherein the low aspect ratio via includes a first seed pattern, which is disposed in the first via hole, and a first conductive pattern that is disposed on the first seed pattern, wherein the first high aspect ratio via includes a second seed pattern, which is disposed in the second via hole, a second conductive pattern, which is disposed on the second seed pattern, a deposition inhibition pattern, which covers at least a portion of the second conductive pattern, and a third conductive pattern, which covers the deposition inhibition pattern, and wherein the deposition inhibition pattern includes a material which is less in surface free energy than the second conductive pattern.