公开(公告)号：US20250120081A1

公开(公告)日：2025-04-10

申请号：US18761611

申请日：2024-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjun AHN ,  Hanhim KANG ,  Donghwan LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes: a mold structure; and a first high aspect ratio via disposed in a second via hole which passes through at least a portion of the mold structure, wherein the low aspect ratio via includes a first seed pattern, which is disposed in the first via hole, and a first conductive pattern that is disposed on the first seed pattern, wherein the first high aspect ratio via includes a second seed pattern, which is disposed in the second via hole, a second conductive pattern, which is disposed on the second seed pattern, a deposition inhibition pattern, which covers at least a portion of the second conductive pattern, and a third conductive pattern, which covers the deposition inhibition pattern, and wherein the deposition inhibition pattern includes a material which is less in surface free energy than the second conductive pattern.

公开(公告)号：US20230232612A1

公开(公告)日：2023-07-20

申请号：US18050179

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanwoo Shin ,  Hyuckjin KANG ,  Donghwan LEE ,  Jeonil LEE ,  Minwu KIM ,  Jungwoo SONG

IPC: H01L29/94

CPC classification number: H01L27/10814 ,  H01L27/10885 ,  H01L27/10855

Abstract: A semiconductor device includes a bit line structure on a substrate, a lower contact plug on a portion of the substrate adjacent to the bit line structure, an upper contact plug including a first metal pattern on the lower contact plug and a second metal pattern contacting an upper surface and an upper sidewall of the first metal pattern, and a capacitor on the upper contact plug. The upper surface of the first metal pattern is above an upper surface of the bit line structure with respect to an upper surface of the substrate.