公开(公告)号：US20230026211A1

公开(公告)日：2023-01-26

申请号：US17814828

申请日：2022-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Ho Park ,  Gyu Ho Kang ,  Seong-Hoon Bae ,  Jeong Gi Jin ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC: H01L23/13 ,  H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor package includes a wiring structure that includes a first insulating layer and a first conductive pattern inside the first insulating layer, a first semiconductor chip disposed on the wiring structure, an interposer that includes a second insulating layer, a second conductive pattern inside the second insulating layer, and a recess that includes a first sidewall formed on a first surface of the interposer that faces the first semiconductor chip and a first bottom surface connected with the first sidewall, where the recess exposes at least a portion of the second insulating layer, a first element bonded to the interposer and that faces the first semiconductor chip inside the recess, and a mold layer that covers the first semiconductor chip and the first element.