公开(公告)号：US20190074211A1

公开(公告)日：2019-03-07

申请号：US15962059

申请日：2018-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Seok MIN ,  Dong Kwon KIM ,  Cheol KIM ,  Young Mook OH ,  Jeong Yun LEE ,  Hyun Ho JUNG

IPC: H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having an active pattern extending in a first direction, a first gate structure and a second gate structure extending in a second direction, intersecting the first direction, to traverse the active pattern, the first gate structure and the second gate structure isolated from each other while facing each other in the second direction, a gate isolation pattern disposed between the first gate structure and the second gate structure, the gate isolation pattern having a void, and a filling insulating portion positioned lower than upper surfaces of the first gate structure and the second gate structure within the gate isolation pattern, the filling insulating portion being connected to at least an upper end of the void.

公开(公告)号：US20220344461A1

公开(公告)日：2022-10-27

申请号：US17516192

申请日：2021-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae Geon JUNG ,  Dong Kwon KIM ,  Cheol KIM

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, a first active pattern that includes a first side wall and a second side wall opposite to the first side wall in a second horizontal direction, a first insulating structure in a first trench extending in the first horizontal direction on the first side wall of the first active pattern, a second insulating structure in a second trench extending in the first horizontal direction on the second side of the first active pattern, and includes a first insulating layer on side walls and a bottom surface of the second trench, and a second insulating layer in the second trench on the first insulating layer, a gate-cut extending in the first horizontal direction on the first insulating structure, and a gate electrode extending in the second horizontal direction on the first active pattern.

公开(公告)号：US20230231024A1

公开(公告)日：2023-07-20

申请号：US17982634

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong Sik SHIN ,  Jeong Yeon SEO ,  Sung Woo KANG ,  Dong Kwon KIM

IPC: H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/7851

Abstract: The semiconductor device including an active pattern on a substrate and extending in a first direction, a gate structure on the active pattern, including a gate electrode extending in a second direction different from the first direction, a source/drain pattern on at least one side of the gate structure, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern, wherein with respect to an upper surface of the active pattern, a height of an upper surface of the gate electrode is same as a height of an upper surface of the source/drain contact, and the source/drain contact comprises a lower source/drain contact and an upper source/drain contact on the lower source/drain contact, may be provided.

公开(公告)号：US20230058116A1

公开(公告)日：2023-02-23

申请号：US17659135

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HONG SIK SHIN ,  Sung Woo KANG ,  Dong Kwon KIM

IPC: H01L29/417

Abstract: A semiconductor device includes a substrate, an active pattern disposed on the substrate and that extends in a first horizontal direction, a field insulating layer disposed on the substrate and that surrounds a sidewall of the active pattern, a gate electrode disposed on the field insulating layer and that extends in a second horizontal direction, a source/drain region disposed on a side of the gate electrode, a first interlayer insulating layer disposed on the field insulating layer and that surrounds a portion of a sidewall of the source/drain region, a second interlayer insulating layer disposed on the first interlayer insulating layer and that surrounds a sidewall of the gate electrode, and a source/drain contact that penetrates through the second interlayer insulating layer and is electrically connected to the source/drain region. The source/drain contact includes a skirt that protrudes from a lower sidewall toward the second interlayer insulating.

公开(公告)号：US20220189870A1

公开(公告)日：2022-06-16

申请号：US17373900

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Dong Kwon KIM ,  Jinwook LEE ,  Jongchul PARK ,  Wonhyuk LEE

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.