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公开(公告)号：US10298214B2
公开(公告)日：2019-05-21
申请号：US15584448
申请日：2017-05-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye-Won Shim , Dong-Uk Park , Phil-Jae Jeon , Sang-Woo Pae , Da Ahn
Abstract: A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.
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