公开(公告)号：US20140149619A1

公开(公告)日：2014-05-29

申请号：US14170086

申请日：2014-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bub-chul JEONG ,  Jaegeun YUN

IPC: G06F13/362

CPC classification number: G06F13/362 ,  G06F13/14 ,  G06F13/36 ,  G06F13/364

Abstract: A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the slave device.

Abstract translation: 提供一种片上系统总线系统及其操作方法。 总线系统包括主设备，从设备和耦合在主设备和从设备之间的互连器。 互连器包括用于控制从主设备提供给从设备的业务的同步/压缩块。 当写请求流量和相应的写数据流量都从主设备提供时，同步/压缩块可以将两个流量传送到从设备。

公开(公告)号：US20150227481A1

公开(公告)日：2015-08-13

申请号：US14616845

申请日：2015-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hee YOO ,  Jaegeun YUN ,  Bub-chul JEONG ,  Dongsoo KANG

IPC: G06F13/364 ,  G06F13/16

CPC classification number: G06F13/364 ,  G06F13/1673 ,  G06F13/4217 ,  G06F21/42 ,  G06F2221/2101

Abstract: A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals.

Abstract translation: 提供了一种系统互连，其包括被配置为基于第一时钟发送多个控制信号的第一信道和被配置为基于第二时钟发送对应于控制信号的多个数据信号的第二信道。 第一通道和第二通道允许非正常的预定范围，并且失调的预定范围表示控制信号的顺序与数据信号的顺序不同，数据信号对应于 控制信号。

公开(公告)号：US20160026603A1

公开(公告)日：2016-01-28

申请号：US14873485

申请日：2015-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegeun YUN ,  Lingling LIAO ,  Bub-chul JEONG

IPC: G06F13/42 ,  G06F13/28 ,  G06F13/40 ,  G06F13/364

CPC classification number: G06F13/4291 ,  G06F1/10 ,  G06F1/3237 ,  G06F13/28 ,  G06F13/364 ,  G06F13/405 ,  G06F13/4054 ,  G06F2213/0038 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/128 ,  Y02D10/151

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract translation: 一种片上系统总线系统，包括：总线，被配置为将片上系统的功能块彼此连接;以及时钟门控单元，连接到总线的接口单元，并且被配置为基本上对在 根据事务检测信号的状态来操作安装在总线上的总线桥装置。